Onkyo TX-SR701 Service Manual page 49

IC BLOCK DIAGRAMS AND DESCRIPTIONS
LC72723M(RDS demodulator)
PIN ARRANGEMENT
V REF 1 16
RDS-ID/READY
MPXIN 2 15 RDCL
Vdda 3 14 RDDA
Vssa 4 LC72723 13 RST
LC72723M
FLOUT 5 12 MODE
CIN 6 11 Vddd
TEST 7 10 Vssd
X OUT 8 9 X IN
Top view
Pin No. Terminal
Function
1 VREF Reference voltage output
2 MPXIN Multiplex signal input
3 Vdda Analog power source (+5V)
4 Vssa Analog grpund
5 FLOUT Sub-carrier output (Filter output)
Sub-carrier input(Comparator output)
6 CIN
7 TEST
Test input
8 XOUT 4.332MHz Crystal connection pin
9 XIN Crystal or external reference signal input
10 Vssd
Digital ground
Digital power supply
11 Vddd
12 MODE Read mode setting
13 RST RDS-ID/RAM reset
14 RDDA RDS data output
RDS clock output (Master mode)/input
15 RDCL
Slave mode)
RDS-ID/
16 RDS-ID/READY output
READY
NJM2595M(5-Input, 3-Output Video Switch)
V+
16
Vin1 13
9
Vin2
20k
Vin3
7
20k
5
Vin4
20k
3
Vin5
20k
BLOCK DIAGRAM
+5V
Vdda
REFERENCE
VOLTAGE
Vssa
MPXIN
ANTIALIASING
FILTER
TEST TEST
MM1512(Y-C mixer circuit)
SW2 SW1 SW5
2
10 14
S1
20k
S4
S2
S3
20k
20k
4 12
6
SW4
SW3
GND
Page 49
V REF
FLOUT CIN
+
V REF
57kHz
BPF
SMOOTHING
(SCF)
FILTER
CLK(4.332MHz)
OSC
X IN X OUT
Bias
Clamp
YIN
6
-6dB
CIN
4
6dB
S5
75Ohm
Amp
Driver
1
Vout1
6dB
S6
75Ohm
Amp
Driver
15 Vout2
6dB
S7
75Ohm
Amp
Driver
11 Vout3
8
V-
TX-SR701/E
CLOCK
PLL
RECOVERY
(57kHz)
(1187.5Hz)
DATA
DECODER
RAM
(128-bit)
RDS-ID
DETECT
Vcc
3
SAG
1
DRV
2
OUT
12dB
5
GND
+5V
Vddd
Vssd
RDDA
RDCL
MODE
RST
RDS-ID/
READY