Kenwood DVR-8100 Service Manual page 12

DVR-8100
QQ
3 7 63 1515 0
Pin No. Pin Name
32 LIN
33 RIN
34 PVDD
35 R
36 PVSS
37 RX4
38 SLAVE
39 RX3
40 TST
41 RX2
42 I2C
43 RX1
44 PDN
4-8 Digital Audio Decoder : CS493263 (X09, IC9)
Pin No. Pin Name
1,12,23 VD(1~3)
2,13,24 DGND(1~3)
3 AUDATA3
4 WR
TE
L 13942296513
5 RD
6 A1
7 A0
8~11
EMA(D7~D0)
14~17
18 CS
19 SCDI0
20 ABOOT
21 EXTMEM
22 SDATAN
25 SCLKN1
26 LRCLKN1
27 CMPDAT
28 CMPCLK
29 CMPREQ
30 CLKIN
31 CLKSEL
32 FLT2
33 FLT1
34 VA
35 AGND
36 RESET
37 DD
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38 DC
39 AUDATA2
40 AUDATA1
41 AUDATA0
42 LRCLK
43 SCLK
44 MCLK
12
CIRCUIT DESCRIPTION
I/O
I Lch Analog Input Pin
I Rch Analog Input Pin
- PLL Power Supply Pin, 4.5V~5.5V
- External Resistor Pin
- PLL Ground Pin
I Receiver channel 4 Pin (Internal biased pin)
Slave Mode Pin
I
"L" : Master mode or Slave mode, "H" : Slave mode
I Receiver channel 3 Pin (Internal biased pin)
Test Pin
I
This pin should be connected to DVSS.
I Receiver channel 2 Pin (Internal biased pin)
Control Mode Select Pin
I
"L" : 4-wire Serial, "H" : I2 C bus
I Receiver channel 1 Pin (Internal biased pin)
I Power Down & Reset Pin
I/O
- Digital positive supplies. Nominally +2.5V
- Digital ground.
0 Unused.
Host Write Strobe, Host Data Strobe, External Memory Write Enable or
I/O
General Purpose Input.
Host Parallel Output Enable, Host parallel R/W, External Memory Output Enable,
I/O
General Purpose Input.
1 Host address bit one or SPI serial control data input.
I Host parallel address bit zero or serial control pin clock.
I/O Data bus (7~0).
I Chip select input.
I/O Serial control data input and output.
I/O Control pin interrupt request, automatic boot enable.
I/O External memory chip select input/output.
I PCM audio data input.
I/O PCM audio input bit clock.
I/O PCM audio input sample rate clock.
I PCM audio data input.
I/O PCM audio input bit clock.
I/O PCM audio input sample rate clock.
I Master clock input.
I DSP clock select.
- Phase locked loop filter.
- Phase locked loop filter.
- Analog positive power supply for clock generator. Nominally +2.5V
- Analog ground for clock generator PLL.
I Master reset input.
I/O This pin should be pulled up with an external 4.7kΩ resistor.
I This pin should be pulled up with an external 4.7kΩ resistor.
O Digital audio output 2.
x ao
y
O Digital audio output 1.
O Digital audio output 0.
. i
I/O Audio output sample rate clock.
I/O Audio output bit clock.
I/O Audio master clock.
8
Pin Description
Pin Description
Q Q
3 6 7 1 3
u163
.
2 9 9 4 2 8
1 5 0 5 8 2 9 9 4
m
co
9 9
2 8 9 9