Denon AVR-5805-UPGRADE Service Manual page 20

QQ
3 7 63 1515 0
Pin description
Pin
CLK System clock
Chip select
CS
CKE Clock enable
A ~ A Address
0 10
BA0,1 Bank select address
RAS Row address strobe
Column address strobe
CAS
WE Write enable
DQM0 ~ 3 Data input/output mask
DQ ~ Data input/output
0 31
V /V Power supply/ground
DD SS
V /V Data output power/ground
DDQ SSQ
NC No Connection
TE
L 13942296513
www
.
http://www.xiaoyu163.com
Name
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Row/column addresses are multiplexed on the same pins.
Row address : RA
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No connection on the device.
x ao u163
y
i
http://www.xiaoyu163.com
2 9
8
Input Function
~ RA , Column address : CA
0 10
after the clock and masks the output.
SHZ
Q Q
3 6 7 1 3 1 5
co
.
20
AVR-5805/AVC-A1XV-UPGRADE
9 4 2 8
~ CA
0 7
0 5 8 2 9 9 4 2 8
m
9 9
9 9