SOYO SY-7VMA-B User Manual page 16

Motherboard Description SY-7VMA-B
composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16M / 32MxN
DRAMs. The DRAM controller can run at either the host CPU bus
frequency (66 /100 /133 MHz) or pseudo-synchronous to the CPU bus
frequency (66/100/133 MHz) with built-in PLL timing control.
The VT8605 system controller also supports full AGP v2.0 capability for
maximum bus utilization including 1x/2x/4x mode transfers, SBA
(SideBand Addressing), Flush/Fence commands, and pipelined grants. An
eight level request queue plus a four level post-write request queue with
thirty-two and sixteen quadwords of read and write data FIFO's
respectively are included for deep pipelined and split AGP transactions. A
single-level GART TLB with 16 full associative entries and flexible CPU /
AGP / PCI remapping control is also provided for operation under
protected mode operating environments. Both Windows-95 VXD and
Windows-98 / Windows 2000 miniport drivers are supported for
interoperability with integrated Savage4 graphics, AGP Expansion
graphics, and DVD-capable multimedia accelerators.
The VT8605 supports two 32-bit 3.3 / 5V system buses (one AGP and one
PCI) that are synchronous / pseudo-synchronous to the CPU bus. The chip
also contains a built-in bus-to-bus bridge to allow simultaneous concurrent
operations on each bus. Five levels (doublewords) of post write buffers are
included to allow for concurrent CPU and PCI operation. For PCI master
operation, forty-eight levels (doublewords) of post write buffers and
sixteen levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chip also supports
enhanced PCI bus commands such as Memory-Read-Line, Memory-Read-
Multiple and Memory-Write-Invalid commands to minimize snoop
overhead. In addition, advanced features are supported such as snoop
ahead, snoop filtering, L1 write-back forward to PCI master, and L1 write-
back merged with PCI post write buffers to minimize PCI master read
latency and DRAM utilization. Delay transaction and read caching
mechanisms are also implemented for further improvement of overall
system performance.
12