3-3.
CPU Signal Descriptions
Pin No.
Signal Name
In/Out
Function
1-4
01- 08
In/Out
Data bus. Also designates RAM address while
signal OP is HIGH.
S
INT
Not used.
6- 18
KI2 - Kl
In/Out
Key input/output signals.
19
SW
In
Power switch input signal.
20- 24
VS- Vl
In
LCD drive voltages. These voltages are
generated by connecting external resistors to
VDD2.
25, 26
050, 051
In/Out
By connecting 56 kohm external resistance
between these terminals, clock pulse is inter-
nally generated.
27 - 72
R1S - R7
Out
LCD display signals.
73
GND
In
o
(zero) volt power source.
74, 75
CE1, CE2
Out
Chip enable signals. CEl selects RAM 1 at
HIGH level while CE2 designates RAM 2 at
HIGH level.
76
VDDl
In
-5.5V input.
77
VDD2
Out
-5.SV output from the LSI.
Stays -S.5V at power ON. Goes to OV at
power-off) or APO (Auto Power-Off).
78, 79
4>1, 4>2
Out
Clock pulses.
80
OP
Out
When the signal is HIGH, the data bus becomes
address bus for RAMs and also becomes the
command code for the optional cassette tape
interface.
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