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Circuit Description
which is integrated on to the IC800. The sync separation and time base
circuits are also integrated on to this chip. Incoming video is stripped
of its line and field sync pulses. The horizontal and vertical syncs are
then derived from the composite sync waveform.
6. Time Base Generator
The line sync is fed to the line time base generator circuit. The line time
base is derived from the master clock oscillator and divider circuit. The
line pulses from the divider are fed into both PLL circuits along with the
sync and flyback pulses. These combine together to produce the line
drive for the line output circuit. Two PLL time constants are used to give
good lock for both fixed, gen-locked syncs, such as from terrestrial
transmission and from weak or variable sync such as VCR.
All controls for the line time base generator are integrated and are
accessed via the I
2
C bus under microcontrol from IC500. These are set
up in the factory by a test software.
6.1 Vertical Time Base
The vertical time base is again generated on chip by the use of the
master clock in conjunction with the separated field sync. The divider
circuit count is controlled by the sync pulse. The counter produces the
pulses to generate the vertical ramp which is in turn fed to a buffer and
then fed out to the field output circuit.
In the event of no valid sync being present then a direct injection mode
is used to continue the function of the ramp generator. This direct mode
then enables vertical scan to be maintained in the event of no signal
being present.
7. RGB Drivers
The RGB video signals are fed out on IC800-(17), -(18), -(19). These
signals are then buffered by the emitter follower circuits TR801, TR802
and TR803 before being fed to the tube base panel. External RGB
signals are also able to be fed into this IC on pins 22, 23 and 24. These
pins are normally fed with RGB levels of 700mVpp signals for nominal
display. The choice of display is determined by the switch pin on
IC800-(21). This is controlled by the output of the teletext chip blank
signal or the blanking signal from the microcontroller for on screen
graphics display or the PERITEL pin 8.
7.1 Auto Grey Scale Tracking
The system also incorporates an automatic grey scale tracking sys-
tem. This removes the need for manual adjustments to set up back-
ground luma levels in high-light and low-light areas on CRTs.
For correct tracking the auto grey scale works on the principal of taking
measurements of the dark current during the field blanking period and
also inserting a peak white signal in that period and setting those
thresholds to control the output stages of the chip. This ensures that the
tube characteristics are constantly being matched by the video output
so that grey scale and picture colour integrity is constantly maintained.
7.2 Beam Limiter
The RGB output gains are also affected by the beam limiter circuit on
IC500. This is to prevent the tube from being damaged or its life
expectancy being shortened by excessive beam current.
The sensing of the beam current is performed at the bottom end of the
DST secondary supplying the EHT focus and G2 voltages to the tube.
The reference point is pin 7 on the DST, this current is sensed as a
change in voltage developed across resistors and fed to the beam limit
sense IC800-(9). This voltage is measured against a reference which
represents maximum beam current. When the sensing level exceeds
the reference then the gain on RGB output amps is reduced, thereby
reducing the beam current. Saturation control, brightness and contrast
are adjusted via the remote control but the nominal levels are preset
in the factory by the I
2
C bus using the microcontroller and test software.
8. System Microcontroller (IC500)
The ST6365 is a dedicated microcontroller for TV control applications.
It has such features as dedicated voltage synthesis tuning control, AFC
control and on-screen graphics display generator. Also it has a
dedicated infrared remote control serial data input. This microcontrol-
2
ler has a dedicated I
C port for communication to other controllable ICs.
The controller clock frequency is 8MHz and this clock speed is
achieved by connecting an 8MHz ceramic resonator across the
oscillator pins 31 and 32 with two 100pF capacitors, C507 and C508,
to ground from each pin. The timing for all functions performed by the
microcontroller including I
2
C bus are taken from this clock.
2 - 2
8.1 Voltage Synthesis
The on-chip voltage synthesis tuning peripheral has been integrated to
allow the generation of a tuning reference voltage. The peripheral is
composed of a 14 bit register that represents the tuning voltage at
pin 1. This voltage is generated using pulse width modulation and bit
rate multiplier techniques.
The 14 bit counter gives 16384 steps which allow a resolution of
approximately 2mV over a tuning voltage range of 32V. Coarse tuning
is achieved by PWM of the 7 most significant bits of the counter, whilst
fine tuning is achieved by BRM (Bit Rate Multiplication) of the 7 least
significant bits of the counter.
The resultant digital pulse train is fed into the base of TR410. This
inverts the pulse train which is then fed into the 3 stage integrator which
integrates the pulse train into a DC voltage.
8.2 AFC Control
The output of the voltage synthesizer can be changed either by the
remote control or the local keyboard. The tuner oscillator is kept on
frequency by the application of AFC. The AFC acts on the voltage
synthesizer via a feedback path. The AFC is generated by IC400. This
voltage is fed back to the AFC pin 9 on the controller. As the tuner
oscillator drifts either up or down so the signal applied to IC400
deviates from the optimum. As a result an error voltage appears on
IC400-(2). This voltage can be either positive or negative with respect
to the optimum voltage. This error voltage is fed to pin 9 of the
microcontroller. This voltage is then digitized. If the digital value is
optimum then no change is made to the synthesized digits. If the digital
value is either side of optimum, then the resultant AFC value is either
added to or subtracted from the synthesizer value.
8.3 Analog Controls
Pins 2 and 5 on the microcontroller are PWM D-A converters. However,
these are only 6 bit resolution which is perfectly acceptable for the
analog functions they perform.
The D-A on pin 2 is used as the electronic volume control for the sound.
The D-A on pin 3 is used for the multi-level voltage control for audio and
video switching of IC400 and IC450. The D-A on pin 4 is used to
produce the threshold level for the AGC to the tuner. The final D-A on
pin 5 is as yet uncommitted. The microcontroller has 3 I/O ports as well
as the dedicated peripheral pins, some of the I/O ports also have
dedicated functions and are listed as their dedicated function, i.e. the
AFC on pin 9 is bit 3 of port B.
8.4 Key Pad Interface
Bits 0-2 and bits 4-5 of port B provide the matrix for the crosswire
keypad.
8.5 Sync Detector/Mute Control
Bit 6 of port B is a sense pin which mutes the sound when text is
displayed and incoming signal is lost. Normally the microcontroller will
mute the sound when the aerial is removed or tuning is off station
because it detects no line lock coincidence.
However, in out-of-hours sync mode, the text chip set detects lack of
sync coincidence and mutes the sound. Bit 0 on port A senses the
status of pin 8 on the peri connector for switching video and sound to
incoming signals on the peri connector.
8.6 Peritel Monitor/OSG Control
Bit 1 on port A monitors the blanking signal on pin 16 of the peri
connector and also the blanking signal from text and OSD sources.
Bit 2 of port A acts as the control line for the switch that acts on SAW450
as described in section 2. Bit 3 is usually linked to ground, however for
System PAL BG/SECAM L/L' this link is omitted.
8.7 Band Switching and LED Driver
Bits 4 to 6 of port A are the band switching outputs which drive the band
switches. Bit 7 of port A is connected to the LED D500. Pins 22 and 25
are OSG display pins whilst pins 26 and 27 are the sync input pins.
Pin 33 is the hardware power-on reset. Pin 34 is the SECAM L/L SAW
selector switch. Pin 35 is IR input line. Pin 36 is BG/DK system select.
8.8 Standby Control/ Sound Mute
Pin 37 is available as a standby line for external use. In normal standby,
the controller shuts down all circuits that provide drive to output stages,
thereby placing the system in quiescent current consumption mode.
Pin 39 is the sound mute output which drives the sound mute transistor
TR5 and TR7. Pins 40 and 41 are the dedicated I
ST 03
2
C bus.
GRUNDIG Service
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