On-Screen Display Process; Video Mode Fetch Process - Toshiba TLP411E Technical Training Manual

9. ON-SCREEN DISPLAY PROCESS

In the on-screen display process, control signals are sup-
plied to the OSD display IC QX43 (mPD6453) through
P901, and the OSD display IC generates character display
signals at the timing determined by VD, HD and clock sup-
plied to the IC separately.
OSL
OSC
OSD
D7 D6 D5 D4 D3 D2 D1 D0
(A) 1 byte command
OSL
OSC
OSD
D7 D6 D5 D4 D3 D2 D1 D0
(A) 2 byte command
OSL
OSC
OSD
D7 D6 D5 D4 D3 D2 D1 D0
(A) 2 byte continuous command
10. VIDEO MODE FETCH
PROCESS
In the video mode fetch process, a status fetch IC Q543
(CXA1315M) fetches the status in the read mode of I
bus (Custom: $45).
2
Fig. 5-9 shows the I C bus read timing diagram. Table 5-4
shows the contents of the video mode signals and the logic.
SDA
SCL
First byte
D7 D6 D5 D4 D3 D2 D1 D0
First byte
D7 D6 D5 D4 D3 D2 D1 D0
Fig. 5-8 Timing diagram for on-screen control signals
2
A7 A6 A1 A0
1 2 7
START Slave address
2
Fig. 5-9 I C bus read timing diagram
Fig. 5-8 shows the timing diagram for the on-screen con-
trol signals.
Second byte
Second byte
D7 D6 D5 D4 D3 D2 D1 D0
Contents of the video mode signals and the logic
Signal
SW0
name
C
Pin No. 2
Q543 V. POL
Positive
(L)
polarity
Negative
(H)
polarity
Read
D7 D6 D1 D0
8 9 1 2 7
Data
ACK
5-8
Second byte
Table 5-4
SW1 SW2
1 9
H. POL H. STATE
Positive
No
polarity
Negative
Yes
polarity
8
STOP
SW3
10
V. STATE
No
Yes