Advanced Chipset Features - Intel 945GC User Manual

Intel 945 Series

4.5.5 Advanced Chipset Features

SLP_S4# Assertion Width
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
► PCI Express Root Port Func
** VGA Setting **
PEG/Onchip VGA Control
On-Chip Frame Buffer Size
DVMT Mode
DVMT/FIXED Memory Size
Boot Display
→←
:Move Enter:Select
↑ ↓
F5: Previous Values
・ SLP_S4# Assertion Width
Available options:[4 to 5 Sec],[3 to 4 Sec],[2 to 3 Sec],[1 to 2 Sec]
・ System BIOS Cacheable
Available options: [Enabled],[Disabled]
・ Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use
this area of system memory usually discusses their memory requirements.
・ Video BIOS Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result.
►
PCI Express Root Port Func
Click <Enter> key to enter its submenu:
PCI Express Port 1(PCIE1)
x PCI Express Port 2
x PCI Express Port 3
x PCI Express Port 4(PCIE2)
PCI-E Compliancy Mode
→←
:Move Enter:Select
↑ ↓
F5: Previous Values
PCI Express Slot 1 ~ PCI Express Slot 4
This option enables or disables the PCI Express port function.
PCI-E Compliancy Mode
This item selects the mode for PCI Express add-on card.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
4 to 5 Sec.
[4 to 5
[Enabled]
[Disabled]
[Disabled]
[Press Enter]
[Auto]
[ 8MB]
[DVMT]
[ 128MB]
[Auto]
+/-/PU/PD:Value
F6: Fail-Safe Defaults
Phoenix - AwardBIOS CMOS Setup Utility
PCI Express Root Port Func
[Auto(4X)] Auto(4X)
Disabled
Disabled
Disabled
[v1.0a]
+/-/PU/PD:Value
F6: Fail-Safe Defaults
- 2 -
Sec.]
Menu Level ►
F10:Save ESC:Exit
F7: Optimized Defaults
Menu Level ►►
F10:Save ESC:Exit
F7: Optimized Defaults
User's Manual
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