HP 9000 Series 310 Service Information Manual page 64

To 010
Addr •••
Buffer.
I/o
Control
51;"011
I/o
Interrupti
010 Interrupt
Un ••
To
I/O
Data
Buff,r.
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>--
>---
/
"-
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010 Control
BUI
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010 Addr... BUI
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1
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1
TLB RAM
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010 Control
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Upper Address Address
Signals
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rno
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1
Buffer Control
I
RAM Parity
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logical Addr ...
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u
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r - - -
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RAM Control
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OD
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Buffered RAM Control
fl
-
Proc ••• or Data
BUI (olio RAM Parity)
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rest Conector
I
Buffer Control
010 Data
Buffers
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RAM Addr... BUI
1/2 t.4EG
RAM Array
With Pority
1
>----1
'-/
DlO Data
BUI
10 MHZ
/0 -""""
-' " ' - -----r
c~~lfr~~rer
Oisable
wi h
TI CUltom
Chip 1
Addr, .. Decode/
Milc. Signola
tlh
TI CUltom
Chip 2
External
I/O Registers;
Interrupt/t.tisc
Signoll
I/OConlrol8 .. lond
Chip [nobl,SUI
r
+-
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i
I
I
L
i
I
-
------+----------L-J--~~-l
Figure 3-9. 98561-66512 Processor Board Block Diagram
54 Functional Description
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1/2 MEG
RAM Array
With Parity
, - -
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