Pioneer XV-DVR9H Service Manual page 167

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• Control Pins
No. Pin Name
26 PC0
27 PC1
28 PC2
30 CMC
55 RESETB
61 SPD/BDB
• IC
No. Pin Name
29, 51 IC (AL)
3 IC (DL)
• Power Supply Pins
TE
L 13942296513
No.
25, 31, 40, 47, 54
24, 33, 35, 42, 49, 52, 53
4, 10, 20, 56, 60
1, 7, 13, 16, 21, 57, 64
• Other Pins
No. Pin Name
41 TpBias0
48 TpBias1
34 RI1
23 XI
22 XO
62 FNSel
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I/O
I
Power class set input
I This pin status will be loaded to Pwr_class bit which allocated to PHY register 4H.
IEEE1394a-2000 chapter [4.3.4.1]
I
Configuration manager capable setting
This pin status will be loaded to Contender bit which allocated to PHY register 4H.
I
0 : Non contender
1 : Contender
Power on reset input
Connect to GND through a 0.1 µF capacitor.
I
0 : Reset
1 : Normal
Speed select (UPD72852GB)
I
0 : MAX. S200
FNSel = 0
1 : MAX. S400
BIAS Detected output (Logical Inverse)
O
0 : BIAS is coming from some port.
FNSel = 1
1 : BIAS is not coming from any port.
I/O
Internally Connected (Low Clamped)
−
Connected to GND.
Internally Connected (Low Clamped)
−
Connected to GND.
Pin Name I/O
−
AV
DD
−
AGND
−
DV
DD
−
DGND
I/O
O Port 0 twisted pair output
O Port 1 twisted pair output
Resistor connection pin 1 for reference current generator
−
Please connect to GND pin through the 9.1 kΩ resistor.
−
Crystal oscillator connection XI
−
Crystal oscillator connection XO
Function Select
I 0 : #61 acts as SPD (UPD72852GB compliant)
1 : #61 acts as BDB
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Function
Function
Q Q
3 6 7 1 3 1 5
Analog power
Analog GND
Digital V
DD
Digital GND
Function
co
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XV-DVR9H
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9 4 2 8
0 5 8 2 9 9 4 2 8
Function
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8
9 9
A
B
C
9 9
D
E
F
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