Ic Block Diagrams And Terminal Descriptions - Integra DTR-5.9 Service Manual

QQ
3 7 63 1515 0

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-7

Q282 : ES29LV160ET-70TG ( 16Mbit CMOS 3.0 Volt-only, Boot Sector Flash Memory )
BLOCK DIAGRAM
Vcc
Vss
WE#
RESET#
A<0:19>
CE#
OE#
BYTE#
PIN LAYOUT
TE
L 13942296513
TERMINAL DESCRIPTION
Pin Name
A0-A19
DQ0-DQ14
DQ15/A-1
CE#
OE#
WE#
www
RESET#
BYTE#
RY/BY#
.
Vcc
Vss
NC
http://www.xiaoyu163.com
RY/BY#
Timer/
Vcc Detector
Counter
Write
Command
State
Register
Machine
Chip Enable
Output Enable
Logic
A15 1
A14 2
A13 3
A12 4
A11 5
A10 6
A9 7
A8 8
A19 9
NC 10
WE# 11 48-Pin Standard TSOP
RESET# 12
NC 13
ES29LV160
NC 14
RY/BY# 15
A18 16
A17 17
A7 18
A6 19
A5 20
A4 21
A3 22
A2 23
A1 24
Description
20 Addresses
15 Data Inputs/Outputs
DQ15 (Data Input/Output, Word Mode) / A-1 (LSB Address Input, Byte Mode)
Chip Enable
Output Enable
Write Enable
Hardware Reset Pin, Active Low
Selects 8-bit or 16-bit mode
x ao u163
y
Ready/Busy Output (N/A SO 044)
i
3.0 volt-only single power supply
Device Ground
Pin Not Connected Internally
http://www.xiaoyu163.com
2 9
8
Analog Bias
Generator
Sector Switches
Y-Decoder
X-Decoder
Q Q
48 A16
3 6 7 1 3 1 5
47 BYTE#
46 Vss
45 DQ15/A-1
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 Vcc
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE#
27 Vss
26 CE#
25 A0
co
.
9 4 2 8
DQ0-DQ15(A-1)
Input/Output
Buffers
Data Latch/
Sense Amps
Y-Decoder
Cell Array
0 5 8 2 9 9 4 2 8
m
DTR-5.9
9 9
9 9