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used as a di rect address.
The nonallowed operation
trap (memory protection violation or nonexistent memory
address) can occur as a resu
I
t of the memory access. In-
dexingisalwaysperformed{with an index register in the
current register block) if bits 12-14 of the analyzed in-
struction are nonzero.
The effective virtual address of
the analyzed instruction is aligned as an integer dis-
placement val ue and loaded into register R, accord-
ing to the instruction addressing type, as follows:
Byte Addressing:
Halfword Addressing:
Word Addressing:
Doubleword Addressing:
Operation codes and mnemonics for the SIGMA 6 instruc-
tion set are shown in Table 5.
Circled numbers in the table
indicate the condition code val ue (decimal) available to the
next instruction after ANALYZE when a direct-addressing
operation code in the corresponding addressing type is analyzed.
Affected: (R), CC
Condition code settings:
2
3
4
Instruction addressi ng type
a
a
a
byte
a
a
1
immediate byte
a
1
a
halfword
1
a
a
word
1
a
1
immediate, word
1
a
doubleword
a
direct addressing (EWO
=
0)
1
indirect addressing (EWO
=
1)
INT
INTERPRET
(Word index alignment)
INTERPRET loads bits 0-3 of the effective word into the
conditi on code, loads bits 4-15 of the effective word
into bit positions 20-31 of register R (and loads a's into
the remai nder of register R), and then loads bits 16-31
of the effective word into bit positions 16-31 of register
Ru 1 (and loads a's into bit positions 0-15 of register Ru 1).
If R is an odd val ue, I NT loads bits 0-3 of the effective
word int0 the condition code, loads bits 16-31 of the ef-
fective word into bit positions 16-31 of register R, and
38
Analyze/Interpret Instructions
Table 5.
ANA L YZE Table for SIGMA 6 Operation Codes
X'n
l
X'OO'+n
X120'+n
X'40'+n
X'60'+n
00
-
AI
TTBS
CBS
01
LCFI®
CI
TBS
CD
MBS
02
LI
-
-
03
-
MI
-
EBS
04
CAll
SF
ANLZ
BDR
05
CAL2
S
CS
BIR
06
CAL3
-
XW
AWM
07
CAL4
-
STS
EXU
08
PLW
CVS
EOR
BCR
09
PSW
CVA
®
OR
BCS
OA
PLM
LM
LS
BAL
OB
PSM
STM
AND
INT
OC
-
-
SIO
RD
OD
LPSD
@
-
TIO
WD
OE
WAIT
TDV
AIO
OF
XPSD
LRP
HIO
MMC
10
AD
AW
AH
LCF
11
CD
CW
CH
CB
12
LD
lW
lH
LB
13
MSP
MTW
MTH
MTB
14
-
-
-
STCF
15
STD
STW
STH
STB
®
16
-
DW
DH
0
PACK 0
17
-
MW
MH
UNPK
18
SD
SW
SH
DS
19
CLM
CLR
-
DA
1A
LCD
LCW
LCH
DD
1B
LAD
LAW
LAH
DM
IC
FSL
FSS
--
DSA
ID
FAL
FAS
-
DC
1E
FDL
FDS
-
DL
IF
FMl
FMS
-
DST
loads OIS into bit positions 0-15 of register R (bits 4-15
of the effective word are ignored in this case).
Affected: (R), (Ru 1), CC
EW
O
_
3
-
CC
EW
4 ._
15 -
R
20 - 31 ;
0 -
R O -
19
EW
16
_
31
-
Rul
16
_
3I
; 0 -
RuI
O
_
15
Condition code settings:
2
3
4
EWO
Example 1, even R field value:
Before execution
EW
X I 1 2345678 I
(R)
xxxxxxxx
(Ru 1)
xxxxxxxx
CC
xxxx
After execution
X I 1 2345678'
X 100000234'
X'00005678'
0001
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