Table of Contents
Advertisement
2. SIGMA 6 SYSTEM ORGANIZATION
The primary el ements in a basic SIGMA 6 system - a centrai
processor, core memory, and input/output processor - are
all designed around a central, double bus structure.
Each primary element of the system operates asynchronously
and semi -independently, automatically overlapping the op-
eration of the other elements (when circumstances permit)
for greater speed. The basic configuration can be expanded
merely by increasing the number of core memory units
(up to four), increasing the number of buses (up to six),
increasing the number of input/output processors (up to
eight), or by increasing the number of central processors.
INFORMATION FORMAT
The basic element of SIGMA 6 information is a 32-bit word,
in which the bit positions are numbered from 0 through 31,
as follows:
A SIGMA 6 word can be divided into two 16-bit parts
(called halfwords) in which the bit positions are numbered
from 0 through 15, as follows:
A SIGMA 6 word can also be divided into four 8-bit parts
(called bytes) in which the bit positions are numbered from
o
through 7, as follows:
Byte 0
Byte 1
Byte 2
Byte 3
Two SIGMA 6 words can be combined to form a 64-bit
element (called a doubleword) in which the bit positions
are numbered from 0 through 63, as follows:
I
:
least
si9ni~cant
ward:
I
32 33 34 35136 37 38 39 40 41 42 43144 45 46 47 48 49 50 5
d
52 53 54 55 56 57 58 59160 61 62 63
Four bits of information can be expressed as a single hexa-
decimal digit. A byte can be expressed as a 2-digit hexa-
decimal number, a halfword as a 4-digit hexadecimal
number, a word as an 8-digit hexadecimal number, and a
doubleword as a 16-digit hexadecimal number.
In this
reference manual, a hexadecimal number is displayed as
a string of hexadecimal digits enclosed by single quotation
marks and preceded by the letter
II
X". For example, the
binary number 01011010 is expressed hexadecimally as
X ' 5A',
8
51 GMA 6 System Organization
CORE MEMOR't'
SIGMA 6 core memory systems use a 32-bit word (four 8-bit
bytes) plus a parity bit as the basic unit of information, All
of memory is directly addressable by the CPU (except for
memory locations 0 through 15)and by the lOPs. The SIGMA6
addressing capabi lity accommodates a maximum memory size
of 131, 072 words (524,288 bytes). Core memory is modular
and is available in increments of 16, 384 words (65,536 bytes),
The main memory for SIGMA 6 is physically organized as a
group of "units", A memory unit is the smallest, logically
complete part of the system. It is the smallest port that
can be logically isolated from the rest of the memory sys-
tem.
A memory unit may consist of up to two physical
memory banks. Each memory bank operates independently
and asynchronously with respect to each other. 128K words
of main memory is comprised of four memory units. The
memory is word, halfword, and byte addressable for both
reading and writing.
Each memory unit has a set of "ports"
that are common to both banks within the unit; that is,
all ports in a given memory unit give access to the bonks
within that unit. The basic system is provided with two
ports, expandable to six.
The memory system has 2-way interleaving capabi lity within
a unit and 4-way interleaving between two adjacent units.
Interleaving increases the probabi lity that a processor can
gain access to a given memory bonk without encountering
interference from other processors: A multiple bonk system
increases the probability that successive memory accesses
may be overlapped. In combination, these two features
provide the SIGMA 6 system with effective memory cycle
times of a fraction of the individual bonk cycle times.
DEDICATED MEMORY LDCATIONS
Memory locations 0 through 319 are reserved by standard
XDS software for dedicated purposes as shown in Table 1.
INFORMATION BOUNDARIES
SIGMA 6 instructions assume that bytes, halfwords, and
doublewords are located in storage according to the
following boundary conventions:
1.
A byte is located in bit positions 0 through 7, 8
through 15, 16 through 23, or 24 through 31 of a word.
2.
A halfword is located in bit positions 0 through 15 or
16 through 31 of a word.
3.
A doubleword is located such that bits 0 through 31 of
the doubleword are contained within an even-numbered
word, and bits 32 through 63 of the same doubleword
must be contained within the next consecutive (odd-
numbered) word.
The various information boundaries are illustrated in Figure 2.
Advertisement
Table of Contents
