Sony DXC-390 Service Manual page 76

IC
QQ
3 7 63 1515 0
CXD1256AR (SONY)
TIMING GENERATOR FOR CCD CAMERA
—TOP VIEW—
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57
58
59
60
61
62
63
64
PIN PIN
I/O SIGNAL I/O
NO. NO.
1 O OSCO 17 O
2 I OSCI 18 O
3 I EF 19 O
4 I ED0 20 O
5 I ED1 21 —
6 I ED2 22 O
7 I SMD1 23 O
8 — GND 24 —
9 I SMD2 25 —
VCT
10 O 26 O
11 I D1 27 O
12 I D2 28 —
13 I D3 29 O
14 I D4 30 O
TE
L 13942296513
15 O A5 31 O
16 O A4 32 O
60 VD
VD
INITIALIZE
59 HD
HD
INITIALIZE
57
CL
63
CK
1/2
64
CK
HIGH PULSE
41, 42
SP1 SP2
DRIVER
, GENERATOR
43 CIRCUIT
SH1
44
SH2
45, 46
DL1 DL2
,
22
RG
37
MCK
38
SHP
39
SHD
26, 27
H1, H2
23
LH1
10
VCT
47
BFG
48, 51
CLP1, CLP4
49, 50
CLP2, CLP3 DECODE
52
PBLK
53
ID
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6-4
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31
30
29
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27
26
25
24
23
22
21
20
19
18
17
PIN PIN
SIGNAL I/O SIGNAL I/O SIGNAL
NO. NO.
V3
A3 33 O 49 I/O CLP2
SG2
A0 34 O 50 I/O CLP3
V4
A1 35 O 51 O CLP4
A2 36 I TEST2 52 O PBLK
GND 37 O MCK 53 O ID
SHP
RG 38 O 54 O WEN
SHD
LH1 39 O 55 I GM
V 40 — GND 56 — V
CC CC
SP1
V 41 O 57 O CL
CC
SP2
H1 42 O 58 I PS
SH1
H2 43 O 59 I HD
SH2
GND 44 O 60 I VD
SUB DL1
45 O 61 I HTSG
V2 DL2
46 O 62 I TEST
V1 CK
47 O BFG 63 O
SG1
48 O CLP1 64 I CK
MODE
SET
ADR. COUNT ADR. COUNT ADR. COUNT
H ROM V ROM ROG ROM
LATCH LATCH LATCH GATE
GATE GATE CONTROL
30, 31, 33, 35
SHUT
GATE COUNTER DECODER
ROM
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INPUTS
CK : NTSC (1820 fH)/PAL (1816 fH) CLOCK
D1 : NORMALLY FIX TO "LOW" LEVEL
COLOR
D2 : /BW SELECT
FIELD
D3 : /FRAME SELECT
NTSC
D4 : (EIA) /PAL (CCIR) SELECT
ED0 - ED2 : SHUTTER SPEED SETTING
EF : (NOT IN USE)
ANALOG PROCESSING
GM :
HD : HORIZONTAL SYNC
HTSG : XSG1, XSG2 CONTROL
OSCI : INVERTER FOR OSCILLATOR
PS : SHUTTER SPEED SELECT (
SMD1, SMD2 : SHUTTER MODE SETTING
VD : VERTICAL SYNC
OUTPUTS
A0 - A5 : (NOT IN USE)
BFG : ENCODER/CHROMA MODULATOR PULSE
CK
: NTSC (1820 fH)/PAL (1816 fH) CLOCK
CL : NTSC (910 fH)/PAL (908 fH) CLOCK
CLP1, CLP4 : CLAMP PULSE
DL1 DL2
, : CLOCK FOR DELAY LINE
H1, H2 : CCD HORIZONTAL REGISTER DRIVE CLOCK
ID : LINE IDENTIFICATION
LH1 : CLOCK FOR LAST CCD VERTICAL REGISTER
MCK : NTSC (910 fH)/PAL (908 fH) CLOCK
OSCO : INVERTER FOR OSCILLATOR
PBLK : BLANKING CLEANING PULSE
RG : RESET GATE PULSE
SG1 SG2
, : CCD ELECTRIC CHARGE READ OUT PULSE
SH1 SH2
, : SELECTION
SHD
SHD, : DATA S/H PULSE
SHP
SHP, : PRE-CHARGE LEVEL S/H PULSE
SP1 SP2
, : COLOR SEPARATION S/H PULSE
SUB
: CCD ELECTRIC CHARGE SUBSTRATE PULSE
V1 V4
- : CCD VERTICAL REGISTER DRIVE CLOCK
VCT
: (NOT IN USE)
WEN : WRITE ENABLE
INPUT/OUTPUT
CLP2, CLP3 : CLAMP PULSE
Q Q
OTHER
3 6 7
TEST, TEST2 : TEST
11 - 14
D1 - D4
3
EF
15 - 20
A0 - A5
55
GM
1
OSCO
2
OSCI
61
HTSG
V1 V4
-
32, 34
SG1 SG2
,
4 - 6
ED0 - ED2
7, 9
SMD1, SMD2
58
PS
u163
2 9 9 4
/DIGITAL PROCESSING
SERIAL
/PARALLEL)
1 3 1 5 0 5 8 2 9
m
co
.
2 8
9 9
9 4 2 8 9 9
DXC-390/390P