ViewSonic VE510+-1 Service Manual page 21

technique is also used to reduce the number of preamplifiers. Two identical 8bit ADC
converters are used to increase the throughput of sub ranging ADC to one conversion per
clock cycle.
Each ADC operates in two-step sub range, i.e. coarse (3 bits) and fine (5 bits). One to
four interpolations is performed in fine conversion step to minimize the number of
preamplifier and to improve differential non-linearity errors (DNL). In addition, in order to
prevent potential error occurred during coarse conversion, digital error correction
technique is also used.
Clock Re-Generator Functional Block Diagram
FIG3-3 Clock Re-Generator
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