ViewSonic VE510+-1 Service Manual page 20

Clock Re-Generator Functional Block Diagram
ADC Block Description
Variable Gain Amplifier (VGA)
The front-end circuit is designed to provide four major functions:
Provide AC coupled interface with single-ended R/G/B input signal, convert single-ended
signal to differential signal, and define common mode voltage.
Define CLAMPING voltage level with respect to ground for image brightness control.
Perform user programmable precision gain amplification.
Provide low impedance differential driver for ADC.
Phase Locked Loop (PLL) and Multi-Phase Generation
The phase locked loop (PLL) generates desired ADC sampling clock frequency (30 MHz
to 80 MHz) from external line clock CKREF. The exact frequency is register
programmable and related to the input line clock CKREF as follows:
Freq (PLL) = Freq (CKREF)* Ndiv <12:0>
To ease the graphic interface, a phase programmable output clock is also generated for
external use. The exact phase delay with respect to VCO output clock is register
programmable and can be formulated as follows:
T DELAY = +Tclk * phase<4:0> / 32
Where is a systematic delay? Due to the periodic nature of the clock, user can practically
program the ADC sampling anywhere with respect to data in the step size of Tclk/32.
ADC
Based on the requirements for this ADC (high speed, low power and small size). The sub
ranging architecture is used to minimize the number of comparators. The interpolation
ViewSonic Corporation
FIG3-2 Clock Re-Generator
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