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I
OEM P
NTEL
RODUCTS AND
• The FLASH BIOS can be updated from a file on a disk;
• The current BIOS code can be copied from the FLASH EEPROM to a disk file as a backup in the event that an
upgrade cannot be successfully completed; and
• The BIOS in the FLASH device can be compared with a disk file to ensure the system has the correct BIOS
version.
FLASH USER AREA
Classic/PCI i486 Baby-AT supports a 4 KB programmable Flash User area located at ED000H-EDFFFH. A
programmer may use this area to display a customized message or to execute a small program. The Classic/PCI i486
Baby-AT BIOS accesses the user area just after completing the POST (Power-On Self-Test) if the setup option is
enabled. The flash user area may be updated by running the FMUP.EXE utility, which expects the update files to
have a .USR extension. Sample programs and instructions are in the file CLSUSER.ZIP on the iPAN bulletin board.
KEYBOARD (AND MOUSE) INTERFACE
An Intel 8742 surface mount micro controller contains the Phoenix Technologies' compatible keyboard/mouse
controller code. An AT style keyboard connector is located on the back panel side of the motherboard. The 5V line on
this connector is protected with a PolySwitch circuit which acts much like a fuse except that it re-establishes the
connection after an over-current condition is removed. While the PolySwitch eliminates the possibility of having to
replace a fuse, care should be taken to turn the system power off before installing or removing a keyboard. As a
manufacturing option, customers whose chassis will allow two PS/2 style connectors, one for mouse and one for
keyboard, can be supported by offering PS/2 configuration instead of AT. The 8742 micro controller code supports
Power-On/Reset (POR), network, and keyboard password protection.
programs contained on the utility disk that ships with the system, the POR password is set via the SETUP program. In
addition, the keyboard controller provides for the following "HOT" key sequences:
• CTRL-ALT-DEL: System software reset. This sequence performs a software reset of the system by jumping to
the beginning of the BIOS code and running the POST operation, excluding memory tests.
• <TBD 1> and <TBD 2>: Turbo mode selection. <TBD 1> sets the system for de-turbo mode (emulation of an 8
MHz 80286 CPU using wait states) and <TBD 2> sets the system for turbo mode (its normal operation at 33
MHz). Changing the Turbo mode may be prohibited by an operating system or application software.
SYSTEM MEMORY
The Classic/PCI i486 Baby-AT Motherboard provides four 36-bit wide SIMM sites for memory expansion with
single/dual sided SIMM modules. The memory array is controlled by the Intel 82424TX CDC, and data buffering is
provided by an Intel 82423TX DPU. The four SIMM sites support 256K x 36, 512K x 36, 1M x 36, 2M x 36, 4M x 36
and 8M x 36 SIMM modules. Minimum memory size is 2 MB, and maximum memory size, using four 8M x 36
SIMM modules, is 128 MB.
Memory is always interleaved in two banks; therefore the SIMM sites must be stuffed in pairs. Memory timing is
designed for 70ns fast page devices, faster DRAMs will operate in the board but will provide no performance
improvement. Parity generation/checking is provided for each 8-bit byte.
SIMMs may be installed in combinations of two or four modules; each two SIMMs within an interleaved bank must be
of the same memory size and type (see the Appendix for a complete list of combinations). There are no jumper settings
required for the memory size configuration, the System BIOS automatically sizes memory and initializes the 82424TX
DRAM controller for appropriate DRAM configuration.
CORE CHIP SET
The core chip set is the Intel Saturn chip set, consisting of one 82424TX Cache/DRAM Controller (CDC), one
82423TX Data Path Unit (DPU) device, and one 82378IB System I/O (SIO) bridge chip. This document will outline the
general functionality, for more detailed information refer to the data sheet for the 82420 PCISet from Intel. The Saturn
chip set provides the following functions:
• CPU reset control
• CPU L1 cache control
• CPU burst mode control
• CPU interface control
• Integrated L2 write-back cache controller with tag comparator
• Page-mode DRAM controller
S
D
ERVICES
IVISION
PRELIMINARY - R
Network and keyboard passwords require
Classic/PCI i486 Baby-AT Motherboard Technical Product Summary • Page 8
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