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Theory of Operation
2-29
Read/Write R13
Bits 0-7 - Non-volatile memory (NVM)
After the computer is powered up, or after the interface clear (IFC) signal is issued, the SCM board
status is as follows:
• High temperature warning off
• Self-test bit enabled
• All pushbutton switch interrupts off
• UPS warning off
• Memory address counters at FFFF hex
Real-Time Clock (RTC) and Non-Volatile Memory (NVM)
The real-time clock (RTC) chip contains 16 four-bit locations that store clock and data information
initially loaded from the lOP. A 32.768 KHz crystal oscillator provides the time base. A 4-bit
multiplexed address/data bus provides
110
for the chip.
Writing to R8 or R12 loads a 4-bit register address in the chip. The RTC data is then accessed by
reads or writes of R9, either reading data from the addressed location or writing data to it. Once the
initial address is accessed, succeeding reads or writes cause automatic increments of the address
(address is complemented). This enables blocks of data to be read or written without updating the
address from the lOP.
The accuracy of the RTC is partially dependent on the configuration, environment, and usage of
the computer. Worst-case clock deviation will vary between 40 seconds per month and 3 minutes
per month depending on the preceding factors.
The non-volatile memory (NVM) chip contains 2048 eight-bit bytes of CMOS RAM used to store
configuration and service data. Writing a 16-bit address to R12 in complemented form loads the
address of the NVM location. The data in that location is then accessed by a read or write of R13.
During power-off states, a nickel-cadmium (NICAD) battery assembly on the SCM provides power
to the RTC and NVM chips for a minimum of 10 days.
The RTC and NVM chips must be disabled when power is coming up or going down. Otherwise,
spurious data could be written onto the chips. When the power supply senses that the power output
is out of specification, it sends an interface clear signal to disable communications with the lOP bus.
This signal is translated on the SCM and disables the chips.
When the chips are disabled, the circuitry enables battery input to the chips, maintaining the
memory data and keeping the clock running. During normal operation, the battery is being charged
by the
+
12V supply.
A sample and hold circuit checks the voltage level of the battery assembly at powerup. When power
is off, a capacitor is charged to the battery level. When power comes back on, the voltage level of
the capacitor is automatically read. If the level is below 3 volts, the RTC and NVM data may be
invalid and should be restored by the operating system. This fault condition is indicated to the lOP
by the RTC/NVM battery fail bit (bit 5 of R2). This bit must be read within four seconds of powerup.
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