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2-28
Theory of Operation
Register Allocations
The SCM is assigned select code 7 (highest priority) because it contains the power fail interrupt.
This makes it impossible for the power fail warning to be locked out by an I/O card with a higher
priority. The register and bit allocations for the SCM select code (SC7) are:
Write RI
Bit 1 - Clear fan high warning; 1
=
clear
Bit 2 - Enable self-test; 1
=
enable, 0
=
disable
Bit 3 - Clear uninterruptible power supply (UPS) warning; 1
=
clear
Bit 4 - Clear key input interrupt; 1
=
clear
Bit 5 - Initiate stack self-test; 1
=
initiate
Bit 7 - ROM DMA enable; 1
=
set address counters to all l' s and set continuous poll response,
enable self-test; 1
=
poll response set, 0
=
clear
Read R2
Bit 0 - Reset; 1
=
RESET switch pressed
Bit 1 - PFW; 1
=
power fail warning
Bit 2 - Fan high; 1 = fan high warning
Bit 3 - Self-test enabled; 1 = self-test enabled
Bit 4 - UPS warning; 1
=
UPS warning
Bit 5 - RTC/NVM battery fail; 1
=
fail (latched at power up)
Bit 12 - Start; 1
=
START switch pressed
Bit 13 - Continuous self-test; 1
=
SELF TEST switch latched on
Bit 14 - Non-maskable interrupt; 1
=
interrupt
Bit 15 - Memory dump; 1
=
MEM DUMP switch pressed
Read R3
Self-identity code (4007 hex)
Read R4 or R6
Loader ROM data
Write R8 or Rl2
RTC/NVM/ROM address
Read R8 or Rl2
Read RTC/NVM/ROM address for testing the data bus. Bit patterns can be written to and read from
this register to make sure there are no faults on the data bus.
Read R9
Bits 0-3 - Real-time clock data (RTC)
Read/Write
RIO
I/O to service processor and service panel
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