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Media processor section
AO_D[0]
AO_SCLK
AO_FSYNC
TO SHEET 5
AO_IEC958
AO_MCLKO
AI_D[0]
VIDEO_MUTE[H]
TO SHEET 2
PHY_CNA
480I[H]
TO SHEET 5
5
B1404
B1405
R1408
R1409
R1410
TL1407
R1411
R1412
R1413
R1414
R1415
R1416
K1407
R1417
4
R1402
R1494
R1495
C1450
X1401
R1419
TL1412
TL1490
VI_D[2-9]
TL1491
VO_D[0-15]
R1420
VIDEO_27M
R1421
R1485
TO
DAC_CVBS_OUT
3
R1422
R1486
DAC_SY_OUT
R1423
R1487
DAC_SC_OUT
SHEET 5
R1424
R1488
DAC_Y_OUT
R1425
R1489
DAC_PB_OUT
R1426
R1490
DAC_PR_OUT
C1452
V3.3V
R1493
K1408
C1453
C1454
D1401
D1402
C1455
C1456
TL1413
TL1414
TL1415
R1491
TL1417
TL1418
TL1419
R1427
TL1420
PHY_DATA[0-7]
TO
R1428
PHY_CTL[1]
R1429
2
PHY_CTL[0]
SHEET 2
R1430
PHY_LREQ
R1431
PHY_LPS
PHY_LINK_ON
PHY_CLK
R1432
TO
DIGI3.3V
D2.5V
B1401
D1.8V
SHEET 5
LC1401
GND
C1401
C1402
C1404
C1405
C1406
C1417
B1402
LC1402
C1408
C1409
C1411
C1412
D5.0V
TO
D1.8V
B1403
LC1403
D2.5V
C1415
C1461
SHEET 5
DIGI3.3V
GND
C1416
C1413
C1414
TO SHEET 3
D3.3V
C1464
C1465
C1466
C1467
C1468
C1469
C1470
C1471
C1472
C1473
C1474
VDDI1.8
TO SHEET 5
GND
1
A
TL1402
TL1437
TL1403
TL1404
TL1489
TL1452
TL1453
TL1454
TL1455
TL1456
TL1457
TL1458
TL1459
RA1401
RA1402
RA1403
RA1404
RA1405
RA1406
K1402
C1442
C1418
C1419
C1420
C1421
C1422
C1423
C1424
C1425
K1403
C1444
K1404
C1427
C1428
C1429
C1430
K1401
K1406
C1463
K1405
C1434
C1435
C1436
C1437
C1438
C1439
C1445
C1446
C1475
TO SHEET 6
TO SHEET 3
B
C
IC1401
Not use
TO SHEET 5
D
E
2-17
2-18
R1471
R1470
R1472
R1469
C1459
R1468
R1467
R1466
R1465
TL1486
TL1485
R1462
R1461
R1460
R1459
R1458
TL1484
TL1483
TL1482
TL1481
R1453
R1452
TL1480
TL1479
TL1478
TL1477
R1451
R1450
RA1411
RA1410
RA1409
RA1408
RA1407
D1403
R1441
C1457
C1458
TO SHEET 5
F
SDRAM_A[14-17]
SDRAM_VREF
SDRAM_CLK_L[1]
SDRAM_CLK[1]
SDRAM_CLK_L[0]
SDRAM_CLK[0]
TO
SDRAM_WE_L
SDRAM_CKE
SHEET 3
SDRAM_RAS_L
SDRAM_CAS_L
SDRAM_DQM[0-3]
SDRAM_DQS[0-3]
SDRAM_A[0-13]
SDRAM_DQ[16-31]
SDRAM_DQ[0-15]
ALE
OE[L]/LDS[L]
UWE[L]/UDS[L]
ELINK_INT[L]
RD/WR[L]
TO
WAIT[L]
DTACK[L]
SHEET 7
CS[1]
CS[0]
MADD[22]
MADD[1-5]
MADD[6-21]
PHY_RESET[L]
TO
SHEET 2
ATA_ADD[0-4]
ATA_DAT[0-15]
ATA_RESET
ATA_DMAACK[L]
ATA_DMARQ
ATA_IORDY
ATA_INTRQ
ATA_DIOR[L]
TO
ATA_DIOW[L]
ATA2_RESET
SHEET 6
ATA2_DMAACK[L]
ATA2_DMARQ
ATA2_IORDY
ATA2_INTRQ
ATA2_DIOR[L]
ATA2_DIOW[L]
ATA2_ADD[0-4]
ATA2_DAT[0-15]
DAC_RST[L]
R1445
K_BUS_CLK
TO
R1446
K_BUS_REQ
R1447
SYS_RESET[L]
R1448
SHEET 5
K_BUS_OUT
R1449
K_BUS_IN
TO
E5_RESET[L]
UART2_TX
UART2_RX
SHEET 7
p10613001a_rev0
SHEET 4
G
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