LG F1200 Service Manual page 34

(3) Baseband Codec (BBC)
Baseband codec is composed of baseband uplink path (BUL) and baseband downlink path
(BDL). BUL makes GMSK (Gaussian Minimum Shift Keying) modulated signal which has In-
phase (I) component and quadrature (Q) component with burst data from DBB. This modulated
signal is transmitted through RF section via air. BDL process is opposite procedure of BUL.
Namely, it performs GMSK demodulation with input analog I&Q signal from RF section, and
then transmit it to DSP of DBB chip with 270.833kHz data rate through BSP.
From TSP
Burst
Buffer 1
From BSP
Burst
Buffer 2
(4) Voltage Regulation (VREG)
There are 7 LDO (Low Drop Output) regulators in ABB chip. The output of these 7 LDOs are as
following table.
VRDBB
VRIO
VRMEM
VRRAM
VRABB
VRSIM
VRRTC
Timing
Control
Cosine
GMSK
Modulator
270 kHz
Figure 23. Baseband Codec Block Diagram
Output Voltage
1.5V
2.8V
2.8V
2.8V
2.8V
2.85
1.5V
Table 9. LDO Output Table
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6-Bit
Offset
DAC Register
10-Bit Low-Pass
Table DAC Filter
16 x 270 kHz
Sine 10-Bit Low-Pass
Table DAC Filter
6-Bit
Offset
DAC Register
Usage
Digital Core of DBB
Peripheral devices
External memory
LCD & peripheral devices
Analog Block of ABB
SIM card driver
RTC & 32kHz-crystal
3. TECHNICAL BRIEF
BULIP
BULIM
BULQP
BULQM