Harman Kardon AVR 70/230 Service Manual page 60

5. PIN DESCRIPTION
PIN NUMBER PIN NAME
23 ~ 26, 22,
A0−A11
29 ~35
20, 21 BS0, BS1
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
DQ0−DQ15
45, 47, 48, 50,
51, 53
19
CS
18
RAS
17
CAS
16
WE
UDQM
39, 15
LDQM
38 CLK
37 CKE
1, 14, 27 V
DD
28, 41, 54 V
SS
3, 9, 43, 49 V
DDQ
6, 12, 46, 52 V
SSQ
36, 40 NC
PRELIMINARY W9864G6JH
FUNCTION
Multiplexed pins for row and column address.
Row address: A0−A11. Column address: A0−A7.
Address
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
Select bank to activate during row address latch time,
Bank Select
or bank to read/write during address latch time.
Data
Multiplexed pins for data output and input.
Input/ Output
Disable or enable the command decoder. When
Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
Row Address
the clock RAS , CAS and WE define the operation
Strobe
to be executed.
Column
Referred to RAS
Address Strobe
Write Enable
Referred to RAS
The output buffer is placed at Hi-Z (with latency of 2)
Input/output when DQM is sampled high in read cycle. In write
mask cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
Clock Inputs
edge of clock.
CKE controls the clock activation and deactivation.
Clock Enable When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside
Ground
DRAM.
Power for I/O Separated power from V
buffer immunity.
Ground for I/O Separated ground from V
buffer immunity.
No Connection
No connection.
- 5 -
DESCRIPTION
, to improve DQ noise
DD
, to improve DQ noise
SS
Publication Release Date: Jan. 25, 2010
Revision P01