Pin Description - Harman Kardon AVR 70/230 Service Manual

2.3 Pin Description

Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open.
Name In/Out
OP_MODE
RSTb
X_IN
X_OUT OUT
P0[2:0] IN/OUT
P11 IN/OUT
P21 IN/OUT
P3[5:4, 1:0] OD IN/OUT
P41 IN/OUT
Explore Microelectronics Inc. Explore Microelectronics Inc. Explore Microelectronics Inc. Explore Microelectronics Inc. Explore Microelectronics Inc. Explore Microelectronics Inc. Explore Microelectronics Inc. Explore Microelectronics Inc. Explore Microelectronics Inc. Explore Microelectronics Inc. Explore Microelectronics Inc. Explore Microelectronics Inc. Explore Microelectronics Inc. Explore Microelectronics Inc.
P50 IN/OUT IN/OUT IN/OUT
P7[4,1:0] IN/OUT
P87 IN/OUT
P90 IN/OUT
Fusiontectronics co., Ltd. Fusiontectronics co., Ltd. Fusiontectronics co., Ltd. Fusiontectronics co., Ltd. Fusiontectronics co., Ltd. Fusiontectronics co., Ltd. Fusiontectronics co., Ltd. Fusiontectronics co., Ltd. Fusiontectronics co., Ltd. Fusiontectronics co., Ltd. Fusiontectronics co., Ltd.
VDD PWR PWR PWR
VSS PWR PWR PWR
Table 2-1 Pin Description
Buffer Type
IN IXDXXP
IN BDUX8P
IN XTL24P
XTL24P
BRXX12P
BRUX8P
BRXX8P
BRXX8P
BRXX8P
BRXX24P BRXX24P BRXX24P
Confidential Confidential Confidential
BRXX8P BRXX8P BRXX8P
BRXX8P
BRXX8P
- - -
-
Internal Use Only Internal Use Only Internal Use Only Internal Use Only Internal Use Only Internal Use Only
Confidential Proprietary
NON-DISCLOSURE AGREEMENT REQUIRED
Chip operation mode.
0: Normal mode
1: ICP (In Circuit Flash Programming) mode
NOTE: The input crystal rate will be 24MHz if this ICP mode is used.
External Reset (active low) with on-chip pull-up. When this pin is asserted
low, the chip is totally reset.
crystal input
crystal output
GPIO port 0 with programmable Open Drain capability.
GPIO port 1 or Keyboard Interrupt inputs with internal 20K pull-up to
VDD
GPIO port 2 with programmable Open Drain capability.
Open Drain I/O port 3. Shared with IIC.
GPIO port 4 or External Interrupt inputs
GPIO port 5 with programmable Open Drain capability. 20 mA drive GPIO port 5 with programmable Open Drain capability. 20 mA drive GPIO port 5 with programmable Open Drain capability. 20 mA drive
Open Drain I/O port 7. P7[1:0] shared with Serial Port. Open Drain I/O port 7. P7[1:0] shared with Serial Port. Open Drain I/O port 7. P7[1:0] shared with Serial Port. P7[4] share with Open Drain I/O port 7. P7[1:0] shared with Serial Port. P7[4] share with
CIR. CIR. CIR.
GPIO port 8 with programmable Open Drain capability. Share with PWM GPIO port 8 with programmable Open Drain capability. Share with PWM GPIO port 8 with programmable Open Drain capability. Share with PWM
For For For
GPIO port 9 with programmable Open Drain capability. GPIO port 9 with programmable Open Drain capability. GPIO port 9 with programmable Open Drain capability.
Digital VDD (3.3V) Digital VDD (3.3V) Digital VDD (3.3V)
Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground
User Guide — EPF011C_UG
Description
6