Sony HCD-VX77 Service Manual page 49

• IC502 MPEG DECODER, MECHANISM CONTROL (M30624MCA-A34FP) (VIDEO Board (1/3))
Pin No. Pin Name
1 SENSE
2 SENSE CLK
3 RESOLUTION
4 CROMA LEVEL
5 DSP CLK
6 TSENS
7 REMOTE IN
8 BYTE
9 CNVSS
10 DSP MUTE
11 CTRL1 (L : DOUBLE)
12 XRESET
13 XOUT
14 VSS
15 XIN
16 VCC
17 NMI
18 SCOR
19 D SENS
20 CL680 INT
21 CL680 HSEL
22 DF LATCH
23 CL680 HRDY
24 680 RESET
25 H. SYNC IN
26 BGP
27 LPH
28 LD ON
29 IIC. CLK
30 IIC. DATA
31 DATA1O
32 DATA1I
33 CLK1
34 RTS1
35 XVLEVEL. DOWN
36 SUBQ DATA
37 SUBQ CLK
38 P. ON
39 BUS XRDY
40 BUS
41 BUS XHOLD
42, 43 BUS
44 BUS XRD
45 V. SYNC
I/O
I Internal state (SENSE) monitor input (IC101)
O Serial data reading clock output (IC101)
O Serial data output (IC101)
O Lach output (IC101)
O Serial data clock output (IC101)
I Not used
I Not used
I External bus width change input (Connected to ground)
– Ground
O Mute output (IC101) "H" : mute
O Double change output (IC101) "L" : double
I System reset input "L" : reset
O Main clock output (10MHz)
– Ground
I Main clock input (10MHz)
– +5V power supply
I Requests mask disable interruption input (Connected to +5V)
I Subcode sync input (IC101)
I Not used
I Video CD interruption input (IC505)
O Video CD select data of the host MPU (IC505)
O Digital filter latch output (IC509)
I Ready signal input for communication to the host MPU (IC505)
O Video CD reset output (IC505) "L" : reset
I H. sync signal input
I BGP output
O Double control output (IC101) "H" : double
O Laser diode ON/OFF output
I/O IIC clock input from master control
I/O IIC data input from master control
O Serial 1 data output (IC505, 509)
I Serial 1 data input (IC505, 509)
O Serial 1 clock output
O
O Fix the video signal output level output
I Serial 2 data input for subcode sync reading
I Serial 2 clock input for subcode sync reading
I Not used
I Not used
I Not used
I Not used
I Not used
I Model selection input "L" : chinese model, "H" : except chinese model
I V sync signal input
Function
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