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HCD-XGV50
Pin No.
Pin Name
74
NVOEL
75
LVS4
76
DRBS
77
DRDQM0
78
DRDQM1
79
IV55
80
NC
81
SYSRST
82
IRDIN
83
NC
84
VDD1
85
V16M
86
DOUT
87
L_CDLRCK
88
LRCK
89
VSS1
90
L_CDDATA
91
PCMD
92
L_CDBCK
93
BCK
94
EMPH
95
L_SQSO
96
SQSO
97
VDD2
98
L_SQCK
99
SQCK
100
SBSO
101
EXCK
102
DATA
103
L_DATA
104
VSS2
105
L_CDXRST
106
XRST
107
MUTE
108
L_XLAT
109
XLAT
110
L_DCLK
111
CLOK
112
L_SENS
113
SENS
114
L_SCLK
115
SCLK
116
VDD3
117
ATSK
118
XUGF
119
XPCK
120
L_GFS
121
GFS
122
VSS3
50
I/O
O
Out enable signal output to memory
—
Ground
O
Bank select address output to memory
O
Lower byte mask of memory
O
Upper byte mask of memory
—
Ground
—
Not used (open)
I
System reset signal input
I
Not used (Connected to ground)
—
Not used (open)
—
Power supply (+2.5V)
I/O
Not used (open)
O
Digital audio data output (Not used)
I
D/A interface, L/R clock input
O
D/A interface, L/R clock output
—
Ground
I
Serial data input from D/A interface
O
Serial data output to D/A interface
I
Bit clock input (2's COMP) from D/A interface
O
Bit clock output (2's COMP) to D/A interface
O
Not used (open)
I
SubQ 80bit and PCM peak level data input
O
SubQ 80bit and PCM peak level data output
—
Power supply (+2.5V)
O
SQSO read out clock output
I
SQSO read out clock input
O
Not used (open)
I
Not used (Connected to ground)
I
Serial data input from CPU
O
Serial data output to CPU
—
Ground
I
System reset signal input (L:reset)
O
System reset signal output (L:reset)
I
Not used (Connected to ground)
O
Latch signal output to CPU
I
Latch signal input from CPU
O
Serial data clock output
I
Serial data clock input
I
SENS signal input
O
SENS signal output
O
SENS serial data read clock output
I
SENS serial data read clock input
—
Power supply (+2.5V)
I/O
Not used (Connected to ground)
O
Not used (open)
O
Not used (open)
I
GPS signal input
O
GPS signal output
—
Ground
Description
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