Sony STR-KSL5 Service Manual page 24

STR-KSL5
Pin No. Pin Name
53 PAGE0
54 BOOT
55 BTACT
56 BST
57 MOD1
58 MOD0
59 EXLOCK
60 VDDI
61 VSS
62 A17
63 A16
64-66 A15-A13
67-69 GP10-GP8
70 VDDI
71 VSS
72-75 D15-D12
76 VDDE
77-80 D11-D8
81 VSS
82-85 A9-A10
86 TDO
87 TMS
88 XTRST
89 TCK
90 TDI
91 VSS
92-97 A8-A3
98,99 D7,D6
100 VDDI
101 VSS
102-105 D5-D2
106 VDDE
107,108 D1,D0
109,110 A2,A1
111 VSS
112 A0
113 PM
114 SD13
115 SD14
116 SYNC
117-119 VSS
120 VDDI
24
I/O
O ERAM page switch (TP1212)
I Not used (Ground)
O Boot mode status display signal (TP1213)
I Boot strap signal input from the system control (IC1601)
I Setting for 256fs (pllx9) (pull up)
I Setting for single chip mode (pull down)
I Lock signal input terminal
— +2.5V
— Ground terminal
O External memory address (TP1214)
O External memory address (TP1215)
O Address signal output to the SRAM (IC1202)
I/O External memory data I/O general purpose port terminal GP
— +2.5V
— Ground terminal
I/O SRAM (IC1202) data signal I/O terminal
— +3.3V
I/O SRAM (IC1202) data signal I/O terminal
— Ground terminal
O Address signal output to the SRAM (IC1202)
O Simple emulation data output (TP1216)
I Simple emulation data entry beginning and the end terminal (TP1217)
I Asynchronous simple BREAK input terminal of emulation (TP1218)
I Simple emulation clock input (TP1219)
I Simple emulation data entry (TP1220)
— Ground terminal
O Address signal output to the SRAM (IC1202)
I/O SRAM (IC1202) data signal I/O terminal
— +2.5V
— Ground terminal
I/O SRAM (IC1202) data signal I/O terminal
— +3.3V
I/O SRAM (IC1202) data signal I/O terminal
O Address signal output to the SRAM (IC1202)
— Ground terminal
O Address signal output to the SRAM (IC1202)
I PLL initialization input from the system control (IC1601)
I Data entry terminal (TP1221)
I Data entry terminal (TP1222)
I Synchronization / asynchronous selection terminal (L:Sync. H:Async.)
— Ground terminal
— +2.5V
Description