Figure 4-35. Gpctr Timing Summary - National Instruments 6034E User Manual

V
SOURCE IH
V
IL
V
IH
GATE
V
IL
V
OH
OUT
V
OL
© National Instruments Corporation
t
gsu
t
out
Source Clock Period
Source Pulse Width
Gate Setup Time
Gate Hold Time
Gate Pulse Width
Output Delay Time

Figure 4-35. GPCTR Timing Summary

The GATE and OUT signal transitions shown in Figure 4-35 are referenced
to the rising edge of the SOURCE signal. This timing diagram assumes that
the counters are programmed to count rising edges. The same timing
diagram, but with the source signal inverted and referenced to the falling
edge of the source signal, would apply when the counter is programmed to
count falling edges.
The GATE input timing parameters are referenced to the signal at the
SOURCE input or to one of the internally generated signals on your device.
Figure 4-35 shows the GATE signal referenced to the rising edge of a
source signal. The gate must be valid (either high or low) for at least 10 ns
before the rising or falling edge of a source signal for the gate to take effect
at that source edge, as shown by t
is not required to be held after the active edge of the source signal.
If you use an internal timebase clock, the gate signal cannot be
synchronized with the clock. In this case, gates applied close to a source
edge take effect either on that source edge or on the next one. This
arrangement results in an uncertainty of one source clock period with
respect to unsynchronized gating sources.
t t
sp
sc
t
gh
t
gw
t 50 ns minimum
sc
23 ns minimum
t
sp
t 10 ns minimum
gsu
t 0 ns minimum
gh
t 10 ns minimum
gw
t 80 ns maximum
out
and t in Figure 4-35. The gate signal
gsu gh
4-39
Chapter 4 Signal Connections
t
sp
6034E/6035E User Manual