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Oki MSM9225B User Manual

Oki MSM9225B User Manual

Can (controller area network) controller
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FEUL9225B-04
MSM9225B
User's Manual
CAN (Controller Area Network) Controller
Oki Electric Industry Co., Ltd.
Ver. 4.0
July 2001

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Summary of Contents for Oki MSM9225B

  • Page 1 FEUL9225B-04 MSM9225B User’s Manual CAN (Controller Area Network) Controller Oki Electric Industry Co., Ltd. Ver. 4.0 July 2001...
  • Page 2 Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range.
  • Page 3 CAN protocol specification (Bosch, V2.0 part B/Active). In this manual, additions and modifications that have been made on the upgrade to the MSM9225B from the MSM9225 are indicated by “ ” on their respective pages. This document is subject to change without notice.
  • Page 4 Data frame automatic transmission enabled for remote frame reception Function/meaning of corresponding bit value Value of the bit Initial value after a reset Additions and modifications that have been made in the MSM9225B Indicated by “ ”.

  • Page 5: Table Of Contents

    MSM9225B User’s Manual Contents Table of Contents Chapter 1 Overview Overview..............................1-1 Features............................... 1-1 Block Diagram............................1-2 Configuration Example..........................1-2 Pin Configuration............................1-3 Pin Descriptions............................1-4 Chapter 2 Register Descriptions Memory Space ............................2-1 Message Memory............................2-3 Message Memory Related Register ......................2-4 2.3.1...
  • Page 6 Serial Mode ............................5-8 5.2.5 Other Timing............................5-9 Apppendixes Appendix A Package Dimensions ........................A-1 Appendix B MSM9225B Memory Map ......................A-2 Appendix C MSM9225B User’s Manual Contents of Revision From 2nd Version to 3rd Version ....A-10 Contents – 2...

  • Page 7: Chapter 1 Overview

    Chapter 1 Overview...

  • Page 8: Overview

    Chapter 1 Overview Chapter 1 Overview 1.1 Overview The MSM9225B is a microcontroller peripheral LSI which conforms to the CAN protocol for high-speed LANs in automobiles. 1.2 Features Conforms to CAN protocol specification (Bosch, V2.0 part B/Active) Maximum of 1 Mbps bit rate...

  • Page 9: Block Diagram

    MSM9225B User’s Manual Chapter 1 Overview 1.3 Block Diagram Bit stream A7-0 Bit timing logic (BTL) logic AD7-0/D7-0 (BSL) PALE PRDW/SRW Transmission PRDY/SWAIT control logic (TCL) WAIT Message Data SCLK memory manage- Error management ment Control logic logic (EML) register...

  • Page 10: Pin Configuration

    MSM9225B User’s Manual Chapter 1 Overview 1.5 Pin Configuration AD3/D3 AD4/D4 AD5/D5 AD6/D6 AD7/D7 PRDY/SWAIT Connect all V pins. Connect all GND pins. Figure 1-3 44-Pin Plastic QFP (Top View) 1 – 3...

  • Page 11: Pin Descriptions

    At the rising edge of the shift clock, SDI pin data is captured. At the falling edge, data is output from the SDO pin. Ready output pin When required by the MSM9225B, a signal may be output to extend the bus cycle until the internal access is completed. Internal access in progress...
  • Page 12 MSM9225B User’s Manual Chapter 1 Overview Table 1-1 Pin Description (continued) Symbol Type Description Microcontroller interface select pins Mode1 Mode0 Interface Parallel mode Separate No address latch signal Mode1, 0 29, 30 buses With address latch signal Multiplexed buses Serial mode Interrupt request output pin When an interrupt request occurs, a “L”...

  • Page 13: Chapter 2 Register Descriptions

    Chapter 2 Register Descriptions...

  • Page 14: Memory Space

    Register Descriptions 2.1 Memory Space The MSM9225B has 256 bytes of memory space for the message memory and control registers. Before starting communication, messages for communication and various control registers must be set. Figure 2-1 shows the configuration of memory space.
  • Page 15 MSM9225B User’s Manual Chapter 2 Register Descriptions Table 2-1 Control Register Configuration Address Symbol Name CANC CAN control register CANI CAN interrupt control register NMES Message box count setting register BTR0 CAN bus timing register 0 BTR1 CAN bus timing register 1...

  • Page 16: Message Memory

    MSM9225B User’s Manual Chapter 2 Register Descriptions 2.2 Message Memory The message memory is the memory for setting and storing messages to be transmitted and received. The message memory consists of 16 message boxes from message box 0 to message box F.

  • Page 17: Message Memory Related Register

    MSM9225B User’s Manual Chapter 2 Register Descriptions 2.3 Message Memory Related Register 2.3.1 Message Control Register (MCR: x0hex) This register performs various controls for a message. Set this register for each message box. The bit configuration is as follows: FRM ARES...
  • Page 18 The MSM9225B detects the transmission priority of all the messages for which the TRQ (transmission request) bit is set to “1”, then transmits the messages in sequence from the one with the highest priority.
  • Page 19 MSM9225B User’s Manual Chapter 2 Register Descriptions (6) Transmission request: TRQ When a message box is used for transmission, write “1” to this bit from the microcontroller. When transmission ends normally, “0” is written to this bit. This means that the TRQ bit is “1” during transmission.

  • Page 20: Identifier 0 (Idr0: X1Hex)

    When the received data length code (hereafter DLC) matches the DLC set in the message box, the number of bytes of data indicated by the received DLC is received and written to the message box. When the received DLC does not match the DLC set in the message box, the MSM9225B operates as follows: - The received DLC is written into the DLC field in the message box.

  • Page 21: Identifier 1 (Idr1: X2Hex)

    MSM9225B User’s Manual Chapter 2 Register Descriptions 2.3.3 Identifier 1 (IDR1: x2hex) This register sets the identifier. The bit configuration is as follows: MSB IDB25 IDB24 IDB23 IDB22 IDB21 IDB20 IDB19 IDB18 IDR1 (x2hex), R/W: R/W Initial Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined...
  • Page 22 MSM9225B User’s Manual Chapter 2 Register Descriptions * The top rows indicate the ID for the extended format setting and the bottom rows indicate the content of message 0 for the standard format setting. MSB IDB17 IDB16 IDB15 IDB14 IDB13...
  • Page 23 MSM9225B User’s Manual Chapter 2 Register Descriptions * The top rows indicate the ID for the extended format setting and the bottom rows indicate the content of message 2 for the standard format setting. IDB1 IDB0 IDR4 (x5hex), R/W: R/W...
  • Page 24 MSM9225B User’s Manual Chapter 2 Register Descriptions * The top rows indicate the content of message 1 for the extended format setting and the bottom rows indicate the content of message 4 for the standard format setting. LSB TMSG1 (x7hex), R/W: R/W...
  • Page 25 MSM9225B User’s Manual Chapter 2 Register Descriptions * The top rows indicate the content of message 3 for the extended format setting and the bottom rows indicate the content of message 6 for the standard format setting. LSB TMSG3 (x9hex), R/W: R/W...
  • Page 26 MSM9225B User’s Manual Chapter 2 Register Descriptions * The content of message 5 for the extended format setting is shown below. LSB TMSG5 (xBhex), R/W: R/W TMSG57 TMSG56 TMSG55 TMSG54 TMSG53 TMSG52 TMSG51 TMSG50 Initial Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined...
  • Page 27 MSM9225B User’s Manual Chapter 2 Register Descriptions * The content of message 7 for the extended format setting is shown below. LSB TMSG7 (xDhex), R/W: R/W TMSG77 TMSG76 TMSG75 TMSG74 TMSG73 TMSG72 TMSG71 TMSG70 Initial Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined...
  • Page 28 MSM9225B User’s Manual Chapter 2 Register Descriptions Notes on Identifier (ID) and Message Priority Priority of message A message has the priority determined by the identifier setting. To determine priority, identifiers of messages are compared from the higher bit, and the identifier (set to “0”) detected first has the higher priority (see the example below).

  • Page 29: Control Registers

    MSM9225B User’s Manual Chapter 2 Register Descriptions 2.4 Control Registers These registers listed below control various operations of CAN. Table 2-4 lists the control registers. Table 2-4 Control Registers Initial Address Symbol Name value Bits 4, 5 and 6 are read-only; bits 2 and 7...

  • Page 30: Can Control Register (Canc: 0Ehex)

    MSM9225B User’s Manual Chapter 2 Register Descriptions 2.4.1 CAN Control Register (CANC: 0Ehex) This register controls the operation of CAN. The bit configuration is as follows: CANC (0Ehex), *R/W: R/W CANA SYNC TIRS INIT used used Initial value: Release initialization mode...
  • Page 31 At reset, TIRS is set to “0”. * See Appendix C “Transmission Failure of MSM9225B” for transmission operation. (3) Bit synchronization: SYNC This bit is used to set the bit synchronization edge to synchronize at the CAN bus.

  • Page 32: Can Interrupt Control Register (Cani: 0Fhex)

    MSM9225B User’s Manual Chapter 2 Register Descriptions 2.4.2 CAN Interrupt Control Register (CANI: 0Fhex) This register controls CAN interrupts. The bit configuration is as follows: CANI (0Fhex), *R/W: R/W MEINT EINTE EINTR EINTT used Initial value: Transmission complete interrupt output...
  • Page 33 MSM9225B User’s Manual Chapter 2 Register Descriptions (3) Error interrupt output enable: EINTE When an error occurs, this bit is used to output error interrupt signal INTE from interrupt pin INT. When EINTE is “0”, an error interrupt signal is not output from the interrupt pin.

  • Page 34: Message Box Count Setting Register (Nmes: 1Ehex)

    2.4.4 CAN Bus Timing Register 0 (BTR0: 1Fhex) The MSM9225B has an internal baud rate prescaler that generates the BTL (Bit Timing Logic) signal by dividing the system clock by a factor of 1 to 64. BTL is the system clock for the communication function.
  • Page 35 MSM9225B User’s Manual Chapter 2 Register Descriptions (1) Baud rate prescaler: BRP5 to BRP0 This is a 6-bit field to set the BTL cycle time of the basic clock for communication operation. Table 2-5 shows the relationship between the bit content and BTL.

  • Page 36: Can Bus Timing Register 1 (Btr1: 2Ehex)

    MSM9225B User’s Manual Chapter 2 Register Descriptions 2.4.5 CAN Bus Timing Register 1 (BTR1: 2Ehex) This register sets the sampling point used for bus timing. Writing to the BTR1 bit is enabled, when the INIT bit of the CAN control register (CANC: 0Ehex) is “1”.
  • Page 37 MSM9225B User’s Manual Chapter 2 Register Descriptions Table 2-8 TSEG2 Setting TSEG22 TSEG21 TSEG20 TSEG2 BTL cycle BTL cycle • • • • • • • • • • • • BTL cycle BTL cycle (3) Bit timing Bit timing is set by CAN bus timing registers 0 and 1 (BTR0, 1). Figure 2-24 shows the relationship between 1 bit time of a message and CAN bus timing.
  • Page 38 MSM9225B User’s Manual Chapter 2 Register Descriptions (4) Resynchronization When an edge of the CAN bus signal is detected in the period of SJW, the internal bit status is shifted for resynchronization as shown in Figure 2-25. 1 bit time...
  • Page 39 MSM9225B User’s Manual Chapter 2 Register Descriptions CAN bus signal Before resynchronization SYNC SJW1 TSEG1 TSEG2 TSEG1 TSEG2 SJW2 SJW2 SYNC SJW1 Sampling Point Sampling Point After resynchronization SYNC SJW1 TSEG1 TSEG1 TSEG2 SJW2 TSEG2 SJW2 SYNC SJW1 Sampling Point Sampling Point The sampling point is shifted by SJW.

  • Page 40: Communication Input/Output Control Register (Tioc: 2Fhex)

    MSM9225B User’s Manual Chapter 2 Register Descriptions 2.4.6 Communication Input/Output Control Register (TIOC: 2Fhex) This register sets the input/output mode and output driver format of output pins Tx0 and Tx1. Writing to the TIOC bit is enabled when the INIT bit of the CAN control register (CANC: 0Ehex) is “1”.
  • Page 41 MSM9225B User’s Manual Chapter 2 Register Descriptions (1) Input/output mode setting: OCMD1 to OCMD0 These bits are used to set the output mode of output pins Tx0 and Tx1 and the input mode of input pins Rx0 and Rx1. Table 2-9 shows the relationship between the bit content and input/output mode.
  • Page 42 MSM9225B User’s Manual Chapter 2 Register Descriptions (2) Output driver format setting: OCPOL, OCTN, OCTP OCPOL is used to set the polarity of output. OCTN is used to set the open drain mode of the Nch transistor of the output driver.

  • Page 43: Group Message Register (Gmr0: 3Ehex, Gmr1: 3Fhex)

    MSM9225B User’s Manual Chapter 2 Register Descriptions 2.4.7 Group Message Register (GMR0: 3Ehex, GMR1: 3Fhex) These are registers to set the group message function. Group Message Function If the group message function is used, a part of an identifier can be masked. This can increase the number of receivable identifiers.

  • Page 44: Group Message Mask Register (Gmsk)

    MSM9225B User’s Manual Chapter 2 Register Descriptions 2.4.8 Group Message Mask Register (GMSK) These are registers to mask the identifier of the message box specified by the group message registers GMR0 and GMR1. Using MnID28 to MnID0 (n = 0, 1), set the bits to mask the identifier. Setting “1” masks the bit, and setting “0”...
  • Page 45 MSM9225B User’s Manual Chapter 2 Register Descriptions Notes on how to set the Group Message function When setting the Group Message (GM) function in the message box that selects the extended format as a frame format, specify the message box numbers consecutively, beginning with the message box with the largest message box number.

  • Page 46: Standby Control Register (Stby: 8Ehex)

    (1) Stop mode: STOP If STOP is set to “1”, the MSM9225B will enter the stop mode when the CAN bus is idle. In stop mode, the contents of the message memory and control registers are held but the oscillator and all circuits stop to save power consumption.

  • Page 47: Can Control Register 2 (Canc2: 8Fhex)

    CANC is “1”. Set the RSTEC bit to “0” after setting it to “1”. When the MSM9225B is in the bus off state, this operation is invalid. (Even if the above operation is done, the error counters are not cleared and the bus off state also is not released.)

  • Page 48: Communication Message Box Number Register (Tmn: 9Ehex)

    MSM9225B User’s Manual Chapter 2 Register Descriptions 2.4.11 Communication Message Box Number Register (TMN: 9Ehex) The message box number when a message is transmitted/received is stored in this register. The bit configuration is as follows: TMN (9Ehex), R/W: R TRSN3 TRSN2 TRSN1 TRSN0...

  • Page 49: Can Status Register (Cans: 9Fhex)

    2.4.12 CAN Status Register (CANS: 9Fhex) This is a register to indicate the error status of the MSM9225B. Bit 6 to bit 4 are flags for the transmitter and bit 1 and bit 0 are for the receiver, and this register is read-only.

  • Page 50: Transmit Error Counter (Tec: Aehex)

    MSM9225B User’s Manual Chapter 2 Register Descriptions 2.4.13 Transmit Error Counter (TEC: AEhex) TEC is a register to indicate the Transmit Error Counter value. This register is read-only. At reset or when in the bus off state, TEC is set to “0000 0000”.

  • Page 51: Can Status Register 2 (Cans2: Behex)

    MSM9225B User’s Manual Chapter 2 Register Descriptions 2.4.15 CAN Status Register 2 (CANS2: BEhex) This is a register to indicate the error contents for when an error occurs. If an error occurs, the corresponding flag is set to “1”. It is set to “0” when “0” is written to it from the microcontroller.

  • Page 52: Bus Off Release Counter (Boco: Bfhex)

    MSM9225B User’s Manual Chapter 2 Register Descriptions (3) Acknowledgment error flag: ACK This bit becomes “1” when an acknowledgment error occurs. At reset or after release of the bus off state, this bit becomes “0”. (4) CRC error flag: CRC This bit becomes “1”...

  • Page 53: Chapter 3 Operational Description

    Chapter 3 Operational Description...

  • Page 54: Operational Procedure

    MSM9225B User’s Manual Chapter 3 Operational Description Chapter 3 Operational Description MSM9225B operation is described below. 3.1 Operational Procedure Procedures to set and operate various communication protocols are indicated below. 3.1.1 Initial Setting Figure 3-1 shows the initial setting procedure.

  • Page 55: Transmit Procedure

    MSM9225B User’s Manual Chapter 3 Operational Description 3.1.2 Transmit Procedure Figure 3-2 shows the transmit procedure. * See Appendix C “Transmission Failure of MSM9225B” for transmission operation. Figure 3-2 Transmit Flowchart 3 – 2...

  • Page 56: Receive Procedure

    MSM9225B User’s Manual Chapter 3 Operational Description 3.1.3 Receive Procedure Figure 3-3 shows the receive procedure. INTpin Figure 3-3 Receive Flowchart 3 – 3...

  • Page 57: Message Box Rewrites During Operation

    MSM9225B User’s Manual Chapter 3 Operational Description 3.1.4 Message Box Rewrites during Operation The procedure to rewrite the Identifier (ID) and Data Length Code (DLC) during operation, excluding the time that initial settings are made for the message boxes, is indicated below. The number of message boxes set in the NMES register at the initial setting is the number of (valid) message boxes that can be rewritten.

  • Page 58: Remote Frame Operation

    MSM9225B User’s Manual Chapter 3 Operational Description 3.1.5 Remote Frame Operation The following two methods are available for transmission after remote frame reception. (1) Automatic response: automatically transmit preset message data in message box (2) Manual response: set message data and then transmit 3.1.5.1...
  • Page 59 MSM9225B User’s Manual Chapter 3 Operational Description Microcontroller (user) operation MSM9225B operation INTpin Figure 3-5 Flowchart of Automatic Response after Remote Frame Reception 3 – 6...

  • Page 60: Manual Response

    In this method, after remote frame reception, the transmit data is set and then transmission begins. Table 3-2 lists the settings of the message control register. * See Appendix C “Transmission Failure of MSM9225B” for transmission operation. Table 3-2 Message Control Register Settings for Manual Response...
  • Page 61 MSM9225B User’s Manual Chapter 3 Operational Description Microcontroller (user) operation MSM9225B operation INTpin INTpin Figure 3-6 Manual Response Operation Flowchart 3 – 8...

  • Page 62: Chapter 4 Microcontroller Interface

    Chapter 4 Microcontroller Interface...

  • Page 63: Serial Interface

    Next, input data to the SDI pin. An internal register captures data in a similar manner to the address capture, at the rising edge of SCLK. When 8 bits of data have been captured, the MSM9225B writes the data to the message memory or control register specified by the address that was received previously, and then increments the address counter by 1.
  • Page 64 MSM9225B User’s Manual Chapter 4 Microcontroller Interface 4 – 2...

  • Page 65: Parallel Interface

    MSM9225B User’s Manual Chapter 4 Microcontroller Interface 4.2 Parallel Interface The following three types of parallel interfaces are available. (1) Address/data separate bus type, no address latch signal (2) Address/data separate bus type, with address latch signal (3) Multiplexed bus type For transfer timings, refer to Section 5.2, “Timing Diagrams”.

  • Page 66: Msm9225B Connection Examples

    MSM9225B User’s Manual Chapter 4 Microcontroller Interface 4.3 MSM9225B Connection Examples The following examples are for recommendation only. Oki does not guarantee any operation on customer’s systems. 4.3.1 Microcontroller Interface 4.3.1.1 Address/Data Separate Bus (No Address Latch Signal) +5 V...

  • Page 67: Address/Data Separate Bus (With Address Latch Signal)

    MSM9225B User’s Manual Chapter 4 Microcontroller Interface 4.3.1.2 Address/Data Separate Bus (With Address Latch Signal) +5 V Microcontroller MSM9225B PALE PRD/SRW CSTCV16M0X11Q WAIT PRDY/SWAIT CSTCV16M0X51Q 4-1, 44-41 A7-0 A7-0 38-31 D7-0 AD7-0/D7-0 10 k +5 V SCLK Mode1 RESET RESET...

  • Page 68: Serial Interface

    MSM9225B User’s Manual Chapter 4 Microcontroller Interface 4.3.1.4 Serial Interface +5 V Microcontroller MSM9225B PALE PRD/SRW If the built-in oscillator circuit is used, connect an external oscillator in the same manner as shown in PRDY/SWAIT WAIT Figure 4-2. 4-1, 44-41...

  • Page 69: Can Bus Interface

    MSM9225B User’s Manual Chapter 4 Microcontroller Interface 4.3.2 CAN Bus Interface 4.3.2.1 Electrically Isolated from Bus Transceiver (PCA82C250) +5 V 6N137 MSM9225B PCA82C250 Open Open CANH 6N137 CANL ANODE Vref Open Open Open Open CATH O.P. Figure 4-6 Electrically Isolated from Bus Transceiver (PCA82C250) 4.3.2.2 Directly Connected to Bus Transceiver (PCA82C250)

  • Page 70: Monitoring The Can Bus

    MSM9225B User’s Manual Chapter 4 Microcontroller Interface 4.3.2.3 Monitoring the CAN Bus Battery +5 V PCA82C252 MSM9225B CANH Open CANL Port Microcontroller Port NERR Port Figure 4-8 Monitoring the CAN Bus 4 – 8...

  • Page 71: Chapter 5 Electrical Characteristics

    Chapter 5 Electrical Characteristics...

  • Page 72: Electrical Characteristics

    MSM9225B User’s Manual Chapter 5 Electrical Characteristics Chapter 5 Electrical Characteristics 5.1 Electrical Characteristics 5.1.1 Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Power Supply Voltage Ta = 25°C –0.3 to +7.0 Input Voltage — –0.3 to V +3.0 Output Voltage —...

  • Page 73: Dc Characteristics

    MSM9225B User’s Manual Chapter 5 Electrical Characteristics 5.1.3 DC Characteristics = 4.5 to 5.5 V, Ta = –40 to +125°C) Parameter Symbol Applicable pin Condition Min. Max. Unit “H” Input Voltage Applies to all inputs — 0.8V +0.3 “L” Input Voltage Applies to all inputs —...

  • Page 74: Ac Characteristics

    MSM9225B User’s Manual Chapter 5 Electrical Characteristics 5.1.6 AC Characteristics Parallel mode = 4.5 to 5.5 V, Ta = –40 to +125°C, f = 16 MHz) Parameter Symbol Condition Min. Max. Unit ALE Address Setup Time — — ALE Address Hold Time —...
  • Page 75 MSM9225B User’s Manual Chapter 5 Electrical Characteristics Serial mode = 4.5 to 5.5 V, Ta = –40 to +125°C, f = 16 MHz) Parameter Symbol Condition Min. Max. Unit CS Setup Time — — CS Hold Time — — SCLK Cycle —...

  • Page 76: Timing Diagrams

    AD7-0/ D7-0 WRDH RDLY PRD/ SR W ARDDLY WRDYL PRDY/SWAIT ARLDLY Note: The PRDY signal may be output depending on the internal state of the MSM9225B. Figure 5-1 Read Access Timing Write access timing A7-0 AD7-0/ D7-0 ARWDLY WRDYL PRDY/SWAIT ARLDLY Note: The PRDY signal may be output depending on the internal state of the MSM9225B.

  • Page 77: Separate Bus/Address Latch Mode

    AD7-0/ D7-0 RDLY WRDH ARDDLY PRD/SRW WRDYL PRDY/SWAIT ARLDLY Note: The PRDY signal may be output depending on the internal state of the MSM9225B. Figure 5-3 Read Access Timing Write access timing WALEH PALE A7-0 don’t care AD7-0/ D7-0 ARWDLY...

  • Page 78: Multiplexed Bus Mode

    PALE AD7-0/ D7-0 RDLY WRDH PRD/SRW ARDDLY WRDYL PRDY/SWAIT ARLDLY Note: The PRDY signal may be output depending on the internal state of the MSM9225B. Figure 5-5 Read Access Timing Write access timing WALEH PALE AD7-0/ D7-0 ARWDLY WRDYL PRDY/SWAIT ARLDLY Note: The PRDY signal may be output depending on the internal state of the MSM9225B.

  • Page 79: Serial Mode

    MSM9225B User’s Manual Chapter 5 Electrical Characteristics 5.2.4 Serial Mode Read access timing WAIT SCLK Don’t Care CSZDLY CSODLY DMY0 DMY1 DMY6 DMY7 PRD/SRW WRDY SRDLY PRDY/SWAIT Note: The SWAIT signal will be output during the interval between address and data transfers.

  • Page 80: Other Timing

    MSM9225B User’s Manual Chapter 5 Electrical Characteristics 5.2.5 Other Timing WRSTL WRSTH RESET WINTL clkcy (XT) clkcy Figure 5-9 Other Timing 5 – 9...
  • Page 81 Appendixes...

  • Page 82: Appendix A Package Dimensions

    The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

  • Page 83: Appendix B Msm9225B Memory Map

    Appendixes Appendix B MSM9225B Memory Map The following is the memory map of the entire memory space of the MSM9225B. The symbols ‘Mn’ (for example, M0MCR, M0MSG0, M0IDR2, etc., n = 0 to 15) correspond to the number of the respective message box among the message boxes 0 to 15.
  • Page 84 MSM9225B User’s Manual Appendixes Name Abbreviated name Address [H] Access Value at reset [H] standard extended standard extended 0020 Message control register M2MCR 0021 Identifier 0 M2IDR0 Undefined 0022 Identifier 1 M2IDR1 Undefined 0023 Message 0 Identifier 2 M2MSG0 M2IDR2...
  • Page 85 MSM9225B User’s Manual Appendixes Name Abbreviated name Address [H] Access Value at reset [H] standard extended standard extended 0040 Message control register M4MCR 0041 Identifier 0 M4IDR0 Undefined 0042 Identifier 1 M4IDR1 Undefined 0043 Message 0 Identifier 2 M4MSG0 M4IDR2...
  • Page 86 MSM9225B User’s Manual Appendixes Name Abbreviated name Address [H] Access Value at reset [H] standard extended standard extended 0060 Message control register M6MCR 0061 Identifier 0 M6IDR0 Undefined 0062 Identifier 1 M6IDR1 Undefined 0063 Message 0 Identifier 2 M6MSG0 M6IDR2...
  • Page 87 MSM9225B User’s Manual Appendixes Name Abbreviated name Address [H] Access Value at reset [H] standard extended standard extended 0080 Message control register M8MCR 0081 Identifier 0 M8IDR0 Undefined 0082 Identifier 1 M8IDR1 Undefined 0083 Message 0 Identifier 2 M8MSG0 M8IDR2...
  • Page 88 MSM9225B User’s Manual Appendixes Name Abbreviated name Address [H] Access Value at reset [H] standard extended standard extended 00A0 Message control register M10MCR 00A1 Identifier 0 M10IDR0 Undefined 00A2 Identifier 1 M10IDR1 Undefined 00A3 Message 0 Identifier 2 M10MSG0 M10IDR2...
  • Page 89 MSM9225B User’s Manual Appendixes Name Abbreviated name Address [H] Access Value at reset [H] standard extended standard extended 00C0 Message control register M12MCR 00C1 Identifier 0 M12IDR0 Undefined 00C2 Identifier 1 M12IDR1 Undefined 00C3 Message 0 Identifier 2 M12MSG0 M12IDR2...
  • Page 90 MSM9225B User’s Manual Appendixes Name Abbreviated name Address [H] Access Value at reset [H] standard extended standard extended 00E0 Message control register M14MCR 00E1 Identifier 0 M14IDR0 Undefined 00E2 Identifier 1 M14IDR1 Undefined 00E3 Message 0 Identifier 2 M14MSG0 M14IDR2...
  • Page 91 (2) Error counter reset: RSTEC (4th Ver) “When the MSM9225B is in the bus off state, this operation is invalid. (Even if the above operation is done, the error counters are not cleared and the bus off state also is not released.)” was added.
  • Page 92 MSM9225B User’s Manual Version 1.0: May 2000 Version 2.0: September 2000 Version 3.0: February 2001 Version 4.0: July 2001 2001 Oki Electric Industry Co., Ltd. FEUL9225B-04...

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