Related Manuals for Oki ML60852A
Summary of Contents for Oki ML60852A
- Page 1 FEAL60852A-02 DATE: OCT. 9, 2001 ML60852A Application Manual USB device controller Version 1.02...
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Page 2: Table Of Contents
ML60852A Application Manual 1. INTRODUCTION --------------------------------------------------------------1 2. EXAMPLES OF USB TRANSFER PROCEDURE---------------------6 3. EXTERNAL INTERFACE------------------------------------------------- 19 4. INTERRUPTS----------------------------------------------------------------- 29 5. OTHER FUNCTIONS------------------------------------------------------- 33 6. HANDLING UNUSED PINS ----------------------------------------------- 35 7. DIFFERENCES IN PIN ASSIGNMENT BETWEEN ML60851 AND ML60852A ------------------------------------------------- 37... - Page 3 Pin description..........................3 1.3. Example of External Connections....................4 1.3.1. Example of connections between MSM66573 (OKI make) and ML60852A ......... 4 1.3.2 Example of connections between H8/3048 (Hitachi make) and ML60852A ........5 EXAMPLES OF USB TRANSFER PROCEDURE................ 6 2.1.
- Page 4 Crystal Connection Pin (XOUT)....................35 6.5. Test Pins (TEST1, TEST2)......................36 DIFFERENCEES IN PIN ASSIGNMENT BETWEEN ML60851 AND ML60852A ....37 Test Pin ⇔ GND (pin 5, pin 17) ....................37 7.1. VCC5 ⇒ DACK1 Pin (pin 18) ...................... 38 7.2.
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Page 5: Introduction
ML60852A INTRODUCTION The ML60852A is a general-purpose device controller conforming to the Universal Serial Bus (USB) Standard Rev.1.1. This LSI contains a USB serial interface engine, a USB transceiver, FIFOs, control and status registers, application interface circuits, and an oscillator circuit, and allows easy realization of a USB system. -
Page 6: Pin Configuration And Description
FEAL60852A-02 1 Semiconductor ML60852A 1.2. Pin Configuration and Description 1.2.1. Pin configuration 44-Pin QFP (Top View) DACK0 D– TEST1 XOUT –CS –DREQ1 –RD –WR ADSEL ALE/PUCTL –RESET 56-Pin LGA (Transparent View) TEST2 –INTR ALE/ DACK1 –RESET PUCTL –DREQ1 ADSEL –RD –WR... -
Page 7: Pin Description
FEAL60852A-02 1 Semiconductor ML60852A 1.2.2. Pin description USB Interface Signal name Polarity Description — Pin for connecting USB Data (+) D– — Pin for connecting USB Data (–) When D+ and D– are indeterminate, it is impossible to write data in the registers that are reset by a USB bus reset. -
Page 8: Example Of External Connections
FEAL60852A-02 1 Semiconductor ML60852A 1.3. Example of External Connections 1.3.1. Example of connections between MSM66573 (OKI make) and ML60852A 3.3 V 220 kΩ 100 kΩ ML60852A MSM66573 Connector ALE/PUCTL 1.5 kΩ P127 22 Ω VBUS AD7 to AD0 D7 to D0 D–... -
Page 9: Example Of Connections Between H8/3048 (Hitachi Make) And Ml60852A
FEAL60852A-02 1 Semiconductor ML60852A 1.3.2. Example of connections between H8/3048 (Hitachi make) and ML60852A 3.3 V 220 kΩ 100 kΩ H8/3048 ML60852 ALE/PUCTL Connector 1.5 kΩ 22 Ω VBUS D– D15 to D8 AD7 to AD0 D– 12 MHz D7 to D0... -
Page 10: Examples Of Usb Transfer Procedure
2.1.1. Setting the operating conditions of ML60852A Carry out the settings of the operating conditions of the ML60852A to suit the system after referring to Chapter 3 “EXTERNAL INTERFACE”. 2.1.2. Settings based on standard request Eleven types of standard requests have been defined in USB Standard Rev. -
Page 11: Control Transfer
USB Specifications and it is used for control transfers. The end point used during a control transfer is EP0. The ML60852A has a built-in 32-byte transmit/receive FIFO for EP0. Depending on the type of request, the control transfer can be a control read transfer, a control write transfer, or a control transfer without data. -
Page 12: Setup Ready Interrupt Procedure
Setup-Ready interrupt has been detected by the device (i.e. a Setup packet has been sent from the host to the device and stored satisfactorily ML60852A’s receive FIFO). Based on the type of request, the application firmware must determine whether the transfer is a Control Read, Control Write, or a Control transfer without a data stage. -
Page 13: Reading Received Data In Receive Packet Ready Interrupt Procedure
ML60852A. The IN block signifies the entry point to an event driven software, where a packet of data has been successfully received and stored in the FIFO of ML60852A. Hence, ML60852A generates an interrupt cause. A typical interrupt service procedure is outlined in this diagram. -
Page 14: Writing Transmit Data In Transmit Packet Ready Interrupt Procedure
2.2.4. Writing transmit data in transmit packet ready interrupt procedure The following flow chart illustrates typical procedures for transmitting data from ML60852A device from the point of view of the application firmware controlling the device. The IN block below, signifies the entry point to an event driven firmware where a transmit interrupt cause has been generated. -
Page 15: Bulk Transfer
In the ML60852A, EP1 through EP4 (when in EP5 mode) or EP1 through EP5 (when in EP6 mode) can be used for bulk transfer. These end points can be allocated individually for both bulk-in and bulk-out. -
Page 16: Packet Ready Interrupt Procedure In Bulk-Out Transfer
The following flow chart illustrates the outline of a typical Bulk-Out transfer from the point of view of the application firmware controlling the ML60852A. The IN block shown below, denotes the entry point to an event driven application firmware where a receive interrupt cause has been generated in response to a data packet successfully received and stored in ML60852A’s end point FIFO. -
Page 17: Packet Ready Interrupt Procedure In Bulk-In Transfer
The following flow chart illustrates a typical procedure for carrying out a Bulk-In transfer from the point of view of an application firmware controller ML60852A. The IN block shown below, denotes the entry point to an event driven firmware where a Transmit Packet Ready interrupt cause has been generated and the firmware should service it. -
Page 18: Interrupt Transfer
“Bulk Transfer”, for the outline flow of interrupt transfer processing. In ML60852A, EP1 through EP4 (when in EP5 mode) or EP1 through EP5 (when in EP6 mode) can be used for interrupt transfer. These end points can be allocated individually for both interrupt-in and interrupt-out. -
Page 19: Isochronous Transfer
In the ML60852A, in 5EP mode, EP4 is available and in 6EP mode, EP4 and EP5 are available for isochronous transfer. For these end points, the transfer direction can be individually specified. The FIFO size of EP4 in 5EP mode is 512 bytes. -
Page 20: Outline Flow Of Isochronous-Out Transfer
The following diagram is an illustration of outline flow of an isochronous-out transfer from the point of view of an application firmware controlling ML60852A. As specified by USB standards, a single packet of isochronous data may be received in each USB frame. As a result, the packet reception process is started with detection of a SOF PID on the USB bus. -
Page 21: Outline Flow Of Isochronous-In Transfer
The following diagram is an illustration of outline flow of an isochronous-in transfer from the point of view of an application firmware controlling ML60852A. As shown below, given that a single packet of isochronous data may be transmitted in each USB frame, the transmission processing procedure starts with detection of a SOF packet on the bus. -
Page 22: Errors In Isochronous-Out Transfer
Although the host does not make a re-transmit request when a CRC error occurs in isochronous transfer, a function for re-transmit can be devised by using the temporary received bytes count register. The ML60852A has temporary received bytes count register for EP4 and EP5. 18/39... -
Page 23: External Interface
3.1.1. ADSEL pin The ML60852A supports the Separate and Multiplex methods of accessing data and address buses. ALE pin determines which of these two methods is used. The Separate method is used when ADSEL is “L”. In this case, address lines are connected to AD6 to AD0 and data lines are connected to AD7 to AD0. -
Page 24: Dma Interface
ML60852A makes –DREQ0 and –DREQ1 inactive. Subsequently, when all the data written into the FIFO has been transmitted and an ACK handshake is received from the host computer, the ML60852A resets again the transmit packet ready bit to “0” and makes –DREQ0 and –DREQ1 active. -
Page 25: Address Modes During Dma Transfer
Address modes during DMA transfer The ML60852A supports two address modes. When the bit D1 of the registers DMA0CON and DMA1CON is “0”, the ML60852A operates in the single address mode, and operates in the dual address mode when this bit is “1”. -
Page 26: Dreq Signal Interval During Single Transfer
FIFO by the DMA controller, the ML60852A automatically sets the packet ready bit. Therefore, there will be no need for the local MCU to access the ML60852A in the middle of DMA transfer by setting the size of data to be transferred to the byte count register of the DMA controller at the beginning of DMA transfer. -
Page 27: Interrupt Interface
1 Semiconductor ML60852A 3.3. Interrupt Interface The ML60852A has an interrupt function. The ML60852A issues an interrupt request to the local MCU by making the –INTR pin active. See Chapter 4 “INTERRUPTS” for the interrupt causes. 3.3.1. Selection of –INTR pin polarity It is possible to select the polarity of the –INTR pin by using D0 of the POLSEL register at address 30h. -
Page 28: Oscillation Circuit
3.4.1. Oscillation frequency In the ML60852A, either 6 MHz or 12 MHz can be selected as the oscillation frequency of the crystal or ceramic resonator. The oscillation frequency is selected by using D6 of the SYSCON register at address 2Fh. -
Page 29: Using A Ceramic Resonator
FEAL60852A-02 1 Semiconductor ML60852A 3.4.2.1. Using a ceramic resonator An example of configuration using a ceramic resonator is shown below. CSTCR6M00G15( )-R0 ML60852A XOUT Ceramic resonator: CSTCR6M00G15( )-R0 of Murata MFG. make (built-in capacitor type) Rf = 1 MΩ Figure 3 Example of oscillator circuit using a ceramic resonator (6 MHz) -
Page 30: Supplying An External Clock
The ML60852A has a function that stops the oscillator circuit to enter the low-power state. If D1 of the SYSCON register at address 2Fh is set to “1” in advance, the ML60852A stops oscillation 2 ms after suspended state interrupt generation. If D1 of the SYSCON register is “0”, oscillation does not stop even after occurrence of the suspended state. -
Page 31: Usb Interface
Series resistors in the D+/D– lines The ML60852A has the D+ and D– lines as the interface with the USB bus. It is necessary to insert series resistors between D+/D– and the USB connector. An example of the circuit near the USB connector is shown below. -
Page 32: Vbus Monitoring
FEAL60852A-02 1 Semiconductor ML60852A 3.5.2. VBUS monitoring The USB requires a system configuration that does not allow the D+ line to be pulled up when VBUS (USB power supply line) is OFF. For more information, refer to Section 7.1.5 “Device Speed Identification”... -
Page 33: Interrupts
ML60852A INTERRUPTS There are 17 types of interrupt causes in the ML60852A. The interrupt causes are assigned to each bit of the registers INTSTAT1 at address 21h, and INTSTAT2 at address 22h, and the corresponding bit becomes “1” when an interrupt cause is generated. Although the –INTR pin is a single line, the local MCU can identify the contents of the interrupt by referring to INTSTAT1 and INTSTAT2. -
Page 34: Setup Ready
When the 8 bytes of setup data are received in the setup stage of control transfer and are properly stored in the setup registers of the ML60852A, the ML60852A sets a “1” in bit D2 (Setup ready) of the register EP0STAT at address 60h. -
Page 35: Transmit Packet Ready
If D0 of the INTENBL2 register at address 25h is set to “1”, the SOF interrupt is enabled. If the ML60852A detects SOF on the USB bus, D0 of the INTSTAT2 register at address 22h is set to “1” and –INTR becomes active. -
Page 36: Usb Bus Reset Assert
The USB bus reset assert interrupt is enabled when a “1” is written to D1 of the register INTENBL2 at address 25h. In this case, when the ML60852A detects an SE0 state for 2.5 µs or more, D1 of the INTSTAT2 register at address 22h is set to “1” and –INTR becomes active. -
Page 37: Other Functions
5.4. Suspend Function The ML60852A goes into the suspend state when the idle state in which there is no bus activity on the USB bus, continues for 3 ms or more. If D3 of the register INTENBL2 at address 25h has already been set to “1”, when the ML60852A detects an idle state for 3 ms or longer, D3 of the register INTSTAT2 at address 22h is set to “1”... -
Page 38: Remote Wakeup
SYSCON register is set to “1” when the time elapsed after the USB bus has entered the idle state is less than 5 ms, the ML60852A waits until the idle state continues for 5 ms or more and then restarts oscillation and outputs the remote wakeup signal onto the USB bus. -
Page 39: Handling Unused Pins
FEAL60852A-02 1 Semiconductor ML60852A HANDLING UNUSED PINS In the ML60852A, there are some pins that are not used depending on the operating mode. The handling of unused pins is described below. 6.1. Bus Access Control Pins-1 (A6 to A0) The bus access control pins-1 (A6 to A0) are not used under the following condition: •... -
Page 40: Test Pins (Test1, Test2)
6.5. Test Pins (TEST1, TEST2) The ML60852A has two test pins (TEST1 and TEST2). These pins are used for testing the LSI in the factory and are not used during normal use. • TEST1, TEST2: Fixed at the “L” level. -
Page 41: Differences In Pin Assignment Between Ml60851 And Ml60852A
7.1. For pin 5 and pin 17, the GND and TEST2 pins have been replaced with each other between the ML60851 and ML60852A. However, the TEST pin is fixed to “L” in normal use, so no change is required. 37/39... -
Page 42: Vcc5 ⇒ Dack1 Pin (Pin 18)
A7 Pin ⇒ ⇒ ⇒ ⇒ –DREQ1 Pin (pin 25) 7.4. This pin is an input pin on the ML60851 but it is an output pin on the ML60852A. Therefore, connect it to the DMA controller when DMA channel 1 is used. - Page 43 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range.