Intel DH61BF Technical Product Specification page 64

Intel Desktop Board DH61BF Technical Product Specification
Table 34. Port 80h POST Codes (continued)
Port 80 Code
0x21
0x23
0x24
0x27
0x28
0x29
0x2A
0x2B
0x31
0x33
0x34
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
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Progress Code Enumeration
MRC entry point
Reading SPD from memory DIMMs
Detecting presence of memory DIMMs
Configuring memory
Testing memory
Exit MRC driver
Start to Program MTRR Settings
Done Programming MTRR Settings
PEIMs/Recovery
Crisis Recovery has initiated
Loading recovery capsule
Start recovery capsule / valid capsule is found
CPU Initialization
CPU PEI Phase
Begin CPU PEI Init
XMM instruction enabling
End CPU PEI Init
CPU PEI SMM Phase
Begin CPU SMM Init smm relocate bases
Smm relocate bases for APs
End CPU SMM Init
CPU DXE Phase
CPU DXE Phase begin
Refresh memory space attributes according to MTRRs
Load the microcode if needed
Initialize strings to HII database
Initialize MP support
CPU DXE Phase End
CPU DXE SMM Phase
CPU DXE SMM Phase begin
Relocate SM bases for all APs
CPU DXE SMM Phase end
Enumerating PCI buses
Allocating resources to PCI bus
Hot Plug PCI controller initialization
Memory
PEI after MRC
I/O Buses
continued