Intel PD6730 Application Note page 14

PD672X/30/32/33 — ZV Port Implementation
Table 3. PC Card, ZV Port, and PD6730/'6832 Pin Assignment (Sheet 2 of 2)
I/O in PC
PC Card PC Card
Card
Pin No. Pin
Mode
23 A6
24–25 A[5:4]
26–29 A[3:0]
33 IOIS16#
46 A17
47 A18
48 A19
49 A20
50 A21
53 A22
54 A23
55 A24
56 A25
60 INPACK#
62 SPKR#
NOTE: 'I' indicates that the signal is an input to the PC Card; 'O' indicates that the signal is an output from the PC Card.
Controller ignores BVD2/SPKR#, IOIS16#, and INPACK# during ZV Port operation.
14
ZV Port Pin I/O in ZV
Name Port Mode
I MCLK
I RESERVED RFU
ADDRESS
I
[3:0]
O PCLK
I Y1
I Y3
I Y5
I Y7
I UV0
I UV1
I UV3
I UV5
I UV7
O LRCLK
O SDATA
PD6730 or PD6730 or
PD6832 PD6832
Socket A Socket B
I 103 178
105, 107 181, 183
109,111, 185,187,
I
113,116 189, 191
O 125 201
O 83 158
O 85 161
O 88 164
O 90 166
O 92 168
O 94 170
O 96 172
O 99 174
O 102 176
O 110 186
O 114 190
Comments
Audio MCLK PCM signal
Tristated by Controller; no
connection in PC Card
Used for accessing PC Card
Pixel clock to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Video data to ZV Port
Audio LRCLK PCM signal
Audio PCM Data signal
Application Note