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ESM-2740/2743
40. POST Codes
POST (hex)
Description
CFh
Test CMOS R/W functionality.
Early chipset initialization:
C0h
Detect memory
C1h
C3h
Expand compressed BIOS code to DRAM
Call chipset hook to copy BIOS back to E000 & F000 shadow
C5h
RAM.
0h1
Expand the Xgroup codes locating in physical address 1000:0
02h
Reserved
03h
Initial Superio_Early_Init switch.
04h
Reserved
1. Blank out screen
05h
2. Clear CMOS error flag
06h
Reserved
1. Clear 8042 interface
07h
2. Initialize 8042 self-test
1. Test special keyboard controller for Winbond 977 series Super I/O
08h
chips.
2. Enable keyboard interface.
09h
Reserved
1. Disable PS/2 mouse interface (optional).
2. Auto detect ports for keyboard & mouse followed by a port & interface
0Ah
3. Reset keyboard for Winbond 977 series Super I/O chips.
0Bh
Reserved
0Ch
Reserved
0Dh
Reserved
Test F000h segment shadow to see whether it is R/W-able or not. If test
0Eh
fails, keep beeping the speaker.
0Fh
Reserved
Auto detect flash type to load appropriate flash R/W codes into the run
10h
time area in F000 for ESCD & DMI support.
11h
Reserved
Use walking 1's algorithm to check out interface in CMOS
12h
circuitry. Also set real-time clock power status, and then check for
override.
13h
Reserved
Program chipset default values into chipset. Chipset default
14h
values are MODBINable by OEM customers.
88 ESM-2740/2743 User's Manual
-Disable shadow RAM
-Disable L2 cache (socket 7 or below)
-Program basic chipset registers
-Auto-detection of DRAM size, type and ECC.
-Auto-detection of L2 cache (socket 7 or below)
swap (optional).
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