Table of Contents
Advertisement
M
X
4
B
M
X
4
B
F
S
B
(
F
r
o
n
t
S
i
d
e
B
F
S
B
(
F
r
o
n
t
S
i
d
e
B
FSB Clock means CPU external bus clock.
CPU internal clock = CPU FSB Clock x CPU Clock Ratio
2
2
I
C
B
u
s
I
C
B
u
s
See SMBus.
I
E
E
E
1
3
9
4
I
E
E
E
1
3
9
4
IEEE 1394 is a low-cost digital interface originated by Apple Computer as a desktop LAN and developed by the IEEE 1394 working
group. The IEEE 1394 can transport data at 100, 200 or 400 Mbps. One of the solutions to connect digital television devices
together at 200 Mbps. Serial Bus Management provides overall configuration control of the serial bus in the form of optimizing
arbitration timing, guarantee of adequate electrical power for all devices on the bus, assignment of isochronous channel ID, and
notification of errors. There are two type of IEEE 1394 data transfer: asynchronous and isochronous. Asynchronous transport is the
traditional computer memory-mapped, load and store interface. Data requests are sent to a specific address and an
acknowledgment is returned. In addition to an architecture that scales with silicon technology, IEEE 1394 features a unique
isochronous data channel interface. Isochronous data channels provide guaranteed data transport at a pre-determined rate. This is
especially important for time-critical multimedia data where just-in-time delivery eliminates the need for costly buffering.
P
a
r
i
t
y
B
i
t
P
a
r
i
t
y
B
i
t
The parity mode uses 1 parity bit for each byte, normally it is even parity mode, that is, each time the memory data is updated,
parity bit will be adjusted to have even count "1" for each byte. When next time, if memory is read with odd number of "1", the parity
error is occurred and this is called single bit error detection.
u
s
)
C
l
o
c
k
u
s
)
C
l
o
c
k
78
O
n
l
i
n
e
M
a
n
u
a
l
O
n
l
i
n
e
M
a
n
u
a
l
Advertisement
Table of Contents
