MB91401
(2) Reset
Parameter
Reset input time
PLL reset input time
Note : tcp is internal CPU and clock cycle period for peripheral module.
INITXI
PLLS
54
Pin
Symbol
After power
trstl
INITXI
supply &
input clock
tprstl
PLLS
stabilization
Conditions
At unusing of PLL
At using of PLL
600
At using of PLL
trstl, tprstl
Prelminary
2004.11.12
Value
Unit Remarks
Min
Max
5 tcp
ns
1
s
1
s