Handling Devices - Fujitsu MB91401 Datasheet

Prelminary
2004.11.12

HANDLING DEVICES

Preventing Latch-up
When a voltage that is higher than V
and the output terminal in CMOS IC or the voltage that exceeds ratings between V
latch-up phenomenon might be caused. If latch-up occurs, the supply current increases rapidly, sometimes
resulting in thermal breakdown of the device. Use meticulous care not to let any voltage exceed the maximum
rating during device operation.
Separation of power supply pattern
Analog PLL (APLL at the following) is installed in this LSI. The power supply for VCO and for digital is separated
in LSI so that the oscillation characteristic of APLL may receive the influence of power supply variation.
Therefore, the power supply is recommended to be separated also on the mounting base.
Separation of power supply pattern (recommended)
Take measures to reduce impedance, for example, by using as wide a power pattern as possible.
The recommendation example is shown as follows.
• For two power supplies (for digital and for VCO)
It is advisable to provide a digital power-supply (a) and VCO power-supply (b) and connect them to the LSI's
equivalents, respectively.
Power
supply
(a)
• For the common power supply
To share a single power-supply for digital and VCO uses, it is advisable to separate the output into the digital
and VCO wiring patternsand connect them to the LSI.
and a voltage that is lower than V
DDE
Figure For 2-power supply (for digital and for VCO)
VDD (for digital)
PLLVDD (for VCO)
Power
PLLVSS
supply
(b)
VSS
are impressed to the input terminal
SS
to V
DDE
LSI
Logic part
APLL
MB91401
is impressed, the
SS
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