Part 4: Appendix
1. CONNECTOR LOCATIONS AND PIN CONFIGURATIONS
1.1 Logic Board
JPG1
JASF1
JIF1 (Parallel interface connector)
Pin No.
Compatible mode
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AUTO FEED XT
15
16
17
18
19
STROBE-RET (GND)
20
DATA1-RET (GND)
21
DATA2-RET (GND)
22
DATA3-RET (GND)
23
DATA4-RET (GND)
24
DATA5-RET (GND)
25
DATA6-RET (GND)
26
DATA7-RET (GND)
27
DATA8-RET (GND)
28
ACKNLG-RET (GND)
29
BUSY-RET (GND)
30
P.E.-RET (GND)
31
32
33
34
35
36
JPOW1
JPGS1
Figure 4-4 Logic Board
Nibble mode
STROBE
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
ACKNLG
BUSY
P.E.
AckDataReq
SELECT
N.C
GND
GND
+5.0V
INIT
ERROR
GND
N.C
+5.0V
SELECT IN
HostClk
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
PrtClk
PrtBusy
Xflag
HostBusy
TBD
Gnd
Gnd
Vcc
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
INIT
DataAvail
TBD
TBD
TBD
1284Active
4-6
JIF2
JIF1
JLF1
JINK1
ECP mode
HostClk
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
PeriphClk
PeriphAck
AckReverse
Xflag
HostAck
TBD
Gnd
Gnd
Vcc
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
Signal Gnd
ReverceReq
PeriphReq
TBD
TBD
TBD
1284Active
S820