Table of Contents
Advertisement
Checkpoint
Beep Code
Code
09h
0Ah
0Bh
0Ch
0Eh
0Fh
10h
11h
12h
13h
Description
Set in-POST flag in CMOS that indicates we
are in POST. If this bit is not cleared by post-
ClearBootFlagJ (AEh), the BIOS on next boot
determines that the current configuration
caused POST to fail and uses default values
for configuration.
Clear the CMOS diagnostic byte (register E).
Check the real-time clock and verify the bat-
tery has not lost power. Checksum the
CMOS and verify it has not been corrupted.
Initialize CPU registers.
Enable CPU cache. Set bits in CMOS related
to cache.
Set the initial POST values of the cache reg-
isters if not integrated into the chipset.
Set the initial POST values of registers in the
integrated I/O chip.
Enable the local bus IDE as primary or
secondary depending on other drives
detected.
Initialize power management.
General dispatcher for alternate register ini-
tialization.
Set initial POST values for other hardware
devices defined in the register tables.
Restore the contents of the CPU control
word whenever the CPU is reset.
Early reset of PCI devices required to disable
bus master. Assumes the presence of a stack
and running from decompressed shadow
memory.
23
Advertisement
Table of Contents
