Acer TM7100 Series Service Manual page 90

Table 2-3 NM2160 Pin Descriptions
Pin name Number
72 FRAME#
65 PAR
67 TRDY#
68 STOP#
69 DEVSEL#
81 IDSEL
71 BCLK
66 BREQ#
88 BGNT#
84 RESET#
70 INTA#
145 CLKRUN#
Clock Interface
93 XTAL1/
14MHZ
92 XTAL2/
17MHZ
I/O
I/O
Frame This active-low signal is driven by the bus master to
indicate the beginning and duration of an access. NM2160 drives
this pin in the Bus Master mode
I/O
Parity Even parity across AD31:0&C/BE3:0# is driven by the bus
master during address and write data phases and driven by
NM2160 during read data phases
I/O
Target ready This active low signal indicates NM2160's ability to
S/T/S
complete the current data phase of the transaction. During a read
cycle TRDY# indicates that valid data is present on AD 31:00.
During a write, it indicates NM2160 is prepared to accept data.
Wait states will be inserted until both TRDY#&IRDY# are asserted
together. Input when NM2160 is in Bus Master
I/O
Stop This active low signal indicates that NM2160 is requesting
S/T/S
the master to terminate at the end of current transaction. Input
when NM2160 is in Bus Master
I/O
Device Select This active low signal indicates that NM2160 has
S/T/S
decoded its address as the target of the current access. Input
when NM2160 is in Bus Master
I
Initialization Device Select This input signal is used as a chip
select during configuration read and write transactions
I
Bus Clock This input provides the timing for all transactions on
PCI bus
O
Bus Request This active-low output is used to indicate the arbiter
T/S
that NM2160 desires use of the bus
I
Bus Grant This active-low input indicates NM2160 that access to
the bus has been granted
I
Reset This active-low input is used to initialize NM2160
O
Interrupt request A This active low "level sensitive" output
O/D
indicates an interrupt request
I/O
Clockrun The master device will control this signal to the
O/D
NM2160, according to the Mobile Computing PCI design guide. If
this signal is sampled high by the NM2160 and the PCI clock
related functions are not completed then it will drive this signal
Low to request the Central Clock Resource for the continuation of
the PCI clock. This function can be Enabled/Disabled through
register GR12 bit 5
I
Oscillator Input This pin is used to feed in a reference clock of
14.31818Mhz from an external oscillator OR a Clock Source to
the internal PLL. NM2160 CR70[5] can be programmed to provide
a 1Xfsc or 4xfsc NTSC sub-carrier frequency for an external
analog Encoder
I
Oscillator Input This pin is used to feed in a reference clock of
17.734480Mhz from an external oscillator OR a Clock Source to
the internal PLL. NM2160 CR70[5] can be programmed to provide
a 1Xfsc or 4xfsc PAL/SECAM sub-carrier frequency for an
external Analog Encoder
Description