Acer TM7100 Series Service Manual page 116

Table 2-6 NS87338VJG Pin Descriptions
Pin No.
/TRK0 35
(Normal Mode)
/TRK0 91
(PPM Mode)
VDDB, C 48, 97
VSSB-E 40, 7,
88, 59
/WAIT 82
/WDATA 37
(Normal Mode)
/WDATA 81
(PPM Mode)
/WGATE 36
(Normal Mode)
/WGATE 80
(PPM Mode)
/WP 34
(Normal Mode)
/WP 90
(PPM Mode)
/WR 16
/WRITE 93
X1 5
/ZWS 1
I/O Description
I
FDC Track 0. This input indicates the controller that the head of the
selected floppy disk drive is at track zero.
I
FDC Track 0. This pin gives an additional Track 0 signal in PPM
Mode when PNF = 0.
Power Supply.
PC87332VJG circuitry.
Ground. This is the ground for the PC87332VJG circuitry.
I
EPP Wait. This signal is used in EPP mode by the parallel port device
to extend its access cycle. It is an active low signal.
O
FDC Write Data. This output is the write precompensated serial data
that is written to the selected floppy disk drive. Precompensation is
software selectable.
O
FDC Write Data. This pin provides an additional Write Data signal in
PPM Mode when PNF=0. (See PE.)
O
FDC Write Gate. This output signal enables the write circuitry of the
selected disk drive. WGATE has been designated to prevent glitches
during power-up and power-down. This prevents writing to the disk
when power is cycled.
O
FDC Write Gate. This pin gives an additional Write Gate signal in
PPM mode when PNF = 0.
I
FDC Write Protect. This input indicates that the disk in the selected
drive is write protected.
I
FDC Write Protect. This pin gives an additional Write Gate signal in
PPM mode when PNF = 0.
I
Write. An active low input to signal a write from the microprocessor to
the controller.
O
EPP Write Strobe. This signal is used in EPP mode as write strobe.
It is active low.
I
Clock. Active clock input signal of 14.318 MHz, 24MHz or 48MHz.
O
Zero Wait State. This pin is the Zero Wait State open drain output pin
when bit 6 of FCR is 0. ZWS is driven low when the EPP or ECP is
written, and the access can be shortened.
This is the 3.3V/5V supply voltage for the