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Advanced Chipset Settings
Configure DRAM Timing by SPD
Hyper Path 3
DRAM Throttling Threshold
Booting Graphic Adapter Priori
PEG Buffer Length
Link Latency
PEG Root Control
PEG Link Mode
Slot Power
High Priority Port Select
4-24
[Enabled]
[Auto]
[Auto]
[PCI Express/PCI]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
[Disabled]
Enable or disable
DRAM timing.
Select Screen
Select Item
+-
Change Option
F1
General Help
F10
Save and Exit
ESC
Exit
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