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• IC Pin Function Description
MAIN BOARD IC801
PD789478GC-A41-8BT-A (SYSTEM CONTROLLER)
Pin No.
Pin Name
1, 2
NC
3 to 5
VLC2 to VLC0
6 to 9
COM0 to COM3
10 to 26
S0 to S16
27
REC
28
AC-CHK
29
CD DOOR
30 to 34
NC
35
A-MUTE
36
CD
37
TAPE
38
AVDD
39
NC
40
CD6V-CHK
41
6V-CHK
42
3V-CHK
43
9V-CHK
44, 45
KEY2, KEY1
46
MODE CHK
47
AGND
48
REMOTE
49
TC-PLAY
50
WP/INI
51
NC
52
C-WRQ
53
C-DOUT
54
C-DIN
55
C-CLK
56
C-DRF
57
C-CE
58
C-FSEQ
59
C-XRT
60
P-CON
61
R-COUNT
62
R-DATA
63
R-CLK
64
R-LAT
65
R-MUTE
66
ISS1
67
ISS2
68
M-BASS
69
IC0
70
XT1
I/O
-
Not used
-
Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
O
Common drive signal output to the liquid crystal display
O
Segment drive signal output to the liquid crystal display
Recording/playback detection signal input terminal
I
"L": playback mode, "H": recording mode
I
AC voltage detection signal input terminal "L": AC IN
I
CD lid close detection switch input terminal "L": close
-
Not used
O
Audio muting on/off control signal output terminal "H": muting on
O
CD function control signal output terminal "H": CD on
O
Tape function control signal output terminal "H": tape on
-
Power supply terminal (+3.3V)
-
Not used
I
Power supply voltage (+6V) for CD block monitoring terminal
I
Power supply voltage (+6V) monitoring terminal
I
Power supply voltage (+3V) monitoring terminal
I
Power supply voltage (+9V) monitoring terminal
I
Front panel key input terminal (A/D input)
I
Model destination setting terminal
-
Ground terminal
I
Remote control signal input from the remote control receiver
I
Tape play detection switch input terminal "L": tape play mode
Interrupt status input terminal
I/O
Output terminal for wake up/Initial reset signal reading
-
Not used
I
Interruption detection signal input from the digital signal processor
I
Serial data input from the digital signal processor
O
Serial data output to the digital signal processor
O
Serial data transfer clock signal output to the digital signal processor
I
Focus on/off detection signal input from the digital signal processor
O
Chip enable signal output to the digital signal processor
I
Synchronizing signal detection signal input from the digital signal processor
O
System reset signal output to the digital signal processor "L": reset
O
Power on/off control signal output terminal "L": standby mode, "H": power on
I
PLL serial count data input from the FM/AM PLL
O
PLL serial data output to the FM/AM PLL
O
PLL serial data transfer clock signal output to the FM/AM PLL
O
PLL chip enable signal output to the FM/AM PLL
O
Tuner muting on/off control signal output to the FM/AM PLL "H": muting on
O
ISS 1 on/off control signal output terminal "H": ISS 1 on
O
ISS 2 on/off control signal output terminal "H": ISS 2 on
O
MEGA BASS on/off control signal output terminal "L": MEGA BASS on
I
Not used
I
Sub system clock input terminal (32.768 kHz)
CFD-E100/E100L
Description
Ver. 1.1
43
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