Specification Clarifications - Intel E5405 - Cpu Xeon Quad Core 2.00Ghz Fsb1333Mhz 12M Lga771 Tray Specification

Specification Clarifications

The Specification Clarifications listed in this section may apply to the following
documents:
• Intel® Xeon® Processor 5400 Series Datasheet.
• Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A:
System Programming Guide.
AX1. Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS)
Invalidation
Issue: Section 10.9 INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS) of the
Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System
Programming Guide will be modified to include the presence of page table structure
caches, such as the page directory cache, which Intel processors implement. This
information is needed to aid operating systems in managing page table structure
invalidations properly.
Intel will update the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 3A: System Programming Guide in the coming months. Until that time, an
application note, TLBs, Paging-Structure Caches, and Their Invalidation (http://
www.intel.com/products/processor/manuals/index.htm), is available which provides
more information on the paging structure caches and TLB invalidation.
In rare instances, improper TLB invalidation may result in unpredictable system
behavior, such as system hangs or incorrect data. Developers of operating systems
should take this documentation into account when designing TLB invalidation
algorithms.
Intel® Xeon® Processor 5400 Series
Specification Update
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