Sony MDS-S50 - Md Player Service Manual page 52

MDS-S50
BD BOARD IC151 CXD2662R
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
Pin No. Pin Name
1 MNT0 (FOK)
2 MNT1 (SHOCK)
3 MNT2 (XBUSY)
4 MNT3 (SLOCK)
5 SWDT
6 SCLK
7 XLAT
8 SRDT
9 SENS
10 XRST
11
SQSY
12
DQSY
13 RECP
14 XINT
15 TX
16 OSCI
17 OSCO
18 XTSL
19 DIN0
20
DIN1
21
DOUT
22
DADTAI
23 LRCKI
24
XBCKI
25
ADDT
26
DADT
27 LRCK
28
XBCK
29 FS256
30 DVDD
31 to 34 A03 to A00
35
A10
36 to 40
A04 to A08
41 A11
42 DVSS
43 XOE
44 XCAS
45 A09
46 XRAS
47 XWE
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
52
I/O
Focus OK signal output terminal "H" is output when focus is on ("L": NG)
O
Not used (open)
O
Track jump detection signal output to the system controller (IC1)
O
Busy monitor signal output to the system controller (IC1)
O
Spindle servo lock status monitor signal output terminal Not used (open)
I Writing serial data signal input from the system controller (IC1)
I (S)
Serial data transfer clock signal input from the system controller (IC1)
I (S)
Serial data latch pulse signal input from the system controller (IC1)
O (3)
Reading serial data signal output to the system controller (IC1)
O (3) Internal status (SENSE) output to the system controller (IC1)
I (S)
Reset signal input from the system controller (IC1) "L": reset
Subcode Q sync (SCOR) output to the system controller (IC1)
O
"L" is output every 13.3 msec Almost all, "H" is output
Digital In U-bit CD format subcode Q sync (SCOR) output to the system controller (IC1)
O
"L" is output every 13.3 msec Almost all, "H" is output
Laser power selection signal input from the system controller (IC1)
I
"L": playback mode, "H": recording mode
O Interrupt status output to the system controller (IC1)
O Magnetic head on/off signal output to the over write head drive (IC181)
I System clock signal (512Fs=22.5792 MHz) input from the oscillator circuit
O System clock signal (512Fs=22.5792 MHz) output terminal Not used (open)
Input terminal for the system clock frequency setting
I
"L": 22.5792 MHz, "H": 45.1584 MHz (fixed at "L" in this set)
I Digital audio signal input terminal when recording mode (for digital optical input)
I Digital audio signal input terminal when recording mode (for digital optical input) Not used
O Digital audio signal output terminal when playback mode (for digital optical output) Not used
I Serial data input from the system controller (IC1)
I L/R sampling clock signal (44.1 kHz) input from the system controller (IC1)
I Bit clock signal (2.8224 MHz) input from the system controller (IC1)
I Recording data input from the A/D, D/A converter (IC500)
O Playback data output to the A/D, D/A converter (IC500)
O L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC500)
O Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC500)
O
Clock signal (11.2896 MHz) output terminal Not used (open)
— Power supply terminal (+3.3V) (digital system)
O Address signal output to the D-RAM (IC153)
O Address signal output to the external D-RAM Not used (open)
O Address signal output to the D-RAM (IC153)
Address signal output to the external D-RAM Not used (open)
O
— Ground terminal (digital system)
O Output enable signal output to the D-RAM (IC153) "L" active
O Column address strobe signal output to the D-RAM (IC153) "L" active
O Address signal output to the D-RAM (IC153)
O Row address strobe signal output to the D-RAM (IC153) "L" active
O Write enable signal output to the D-RAM (IC153) "L" active
Description