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Group I, Extended
The two registers in this group, F and Pµ, are addressed by
the hardware during the R and W portions of the time
slice. As described previously, these "housekeeping"
functions overlap the E portions of adjoining time slices.
The adjoining time slice may be addressing other file
registers via minor-cycle-oriented µl's at the same time
that the hardware needs to have access to F and Pµ.
Because of this, F and Pµ are set apart in this special
group. Of course, F and Pµ may also be addressed by µl's,
but NOT during the minor cycles that coincide with the
overlapping Rand W housekeeping functions.
Group II, Extended
These "common block" registers serve all processor states
and encompass divergent functions. The Console Address,
Console Data, ATC, and PE registers are set
asynchronously by the hardware; that is, their setting is
not related to major-cycle timing. Console Address and
Console Data, for example, are set manually from the
System Control Panel -
definitely an asynchronous
function. The setting of BUSY-ACTIVE by the hardware
(via 1/0 Request or Attention) is also asynchronous,
although the µI-implemented set/reset is synchronous.
The CSS register, on the other hand, is set only by the
!hardware, but such setting is always related to minor-cycle
timing.
.A second important distinction in this register group is
that, of the ten registers, four are definitely bit-oriented
with respect to setting and clearing: B/A, T, C, and PM.
All of the registers, however, are read synchronously.
Even Console Address and Console Data, the reading of
which is initiated by pressing the CONSOLE RUN button,
are read during the major cycle assigned to the Console
state.
Group 111, Extended
The registers in this group are contained on the PC boards
for the associated 1/0 processor state. The inbound (read)
registers are set asynchronously by the 1/0 device and
read synchronously by the processing unit. The outbound
(write) registers are set synchronously by the processing
unit and read asynchronously by the 1/0 device. (The
device, of course, acts through an adapter or controller,
but this does not alter the asynchronous character of the
operation.)
Table 1-2. Register File IC's
Register
Register Name
Group
or Number
Description
Quantity
Comments
Basic
0-32
1 x 256·-bit addressable array; 1 bit of
16
8 Register Select Lines:
File
256 registers (32 x 8) per IC
3 - Processor ( 1 of 8)
5 - Reg. No. (1 of 32)
Grp I
F(O),P(1)
4 x 16-bit addressable array; 4 bi ts of
4
4 Register Select Lines:
Extended
Reg 0, 1 for 8 processors per IC
3 - Processor (1 of 8)
1 - Reg. No. (1 of 2)
Grp II
Console Data (N),
Dual D-type FF's, edge-triggered:
8 each
2 bits per IC.
Extended
Console Address (M)
preset and preclear inputs
Busy/Active (B/A)
Same as above
8
Real-Time Clock
4-bit binary counter
4
Overflow every 1092 seconds.
(RTC)
Others
4 FF's per IC; no preset or preclear
4 each
Exceptions: PM - 2 IC's (8 bits)
inputs
BC - 3 IC's (9 bits)
Grp Ill
Extended
Comm Processor
Read Data/ Address
Quad 2-input mplxr
4
4 bits of Data or Addr per IC
Write Data
4 FF's per IC;
4
no preset or pre-
Write Address
clear inputs
4
Basic Data
Channels 1
&
2:
8-bit, double-rank registers;
Bus-Out
4-bit bistable latch
2 each
quantity doubled to allow 16-
Bus-In
See "Write Data"
2 each
bit transfers with presence of
BDC1
Tag-Out
See "Write Data"
2
Channel Control
See "Console Data"
3
4 with Assy/Disassy option.
Byte Count
4-bit binary counter
4
Disc Processor:
See "Write Data"
4
Multi-purpose register; function
depends upon reg. addr. selected.
1-14
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