Table of Contents
Advertisement
The first half byte of the op code (bits 0-3) determines the
format of the instruction performed (one address, two
address, etc.) and the method of addressing used (Figure
1-10). If all four bits are present, the instruction is a
command instruction. From there the bits are broken into
two groups (bits
0-1
and bits 2-3). If both bits in either
g1oup are present, the instruction is a one address instruc-
tion; if neither group has both bits present, the instruction
is a two address instruction. If a bit is present in either of
the groups in a two address instruction or in the bit-absent
group of a one address instruction, the address is indexed
(Figure 1-10).
Instructions
The second half byte (bits 4-7) of the op code determines
the actual operation performed. Use of the Q code and
control code depend upon the operation being performed.
The complete instruction set performed by the CPU is
shown in Figure 1-11.
1-14
Number
Op Code
of Bytes in
B Field
Bits
Address
Address
01
23
T
2
Direct
()()
I
00
' 1
Indexed XR1
01
I
01
1
Indexed XR2
10
I
10
No address
11
I
11
Figure 1-10. Determining Instruction Format
A Field
Address
Direct
Indexed XR1
Indexed XR2
No address
Advertisement
Table of Contents
