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E~CDIC
0123
Bits
1100
1101
1110
1111
4567
~
BA
B
A
h
h
()()()()
•q,
'0001
1
A
J
1
0010
2
B
K
s
2
0011
21
c
L
T
3
0100
4
D
M
u
4
0101
4 1
E
N
v
5
0110
42
F
0
w
6
0111
421
G
p
x
7
1000
8
H
a
y
8
1001
8
1
I
R
z
9
*Card Code for Numeric Zero is A Only
Figure 1-4. Card Code and EBCDIC Conversion Chart
CPU OPERATION
Bridge Basic Storage Module
The bridge basic storage module (BSM) is a ferrite core
storage unit, available.in three basic sizes:
1.
8,192 byte (9 bit) readout.
2.
16,384 byte (9 bit) readout.
3.
32,768 byte (9 bit) readout.
These capacities are commonly called 8K 9 bit, 16K 9 bit,
and 32K 9 bit. The 24K 9 bit or 32K 9 bit capacities can
be obtained by chaining two BSMs together or by using one
32K 9 bit BSM. Check circuitry causes an invalid address
for addresses above the rated capacity.
Physically, the BSM is a separately packaged unit that
mounts in the space provided for an MST-1 board. It con-
tains a core array, timing and control circuits, a drive system,
and a sense/inhibit system. The BSM also includes the
storage data register (SDR), but does
not
contain a storage
address register (SAR) .
Communication between the system and storage is via
interface lines which transfer address information, input
data, output data, and control signals. Interface circuits
are compatible with MST-I circuit technology. Within the
BSM some SLT circuits are used.
Each storage cycle (read cycle or write cycle) takes approx-
imately 1.2 us. Once it has been started by a read call/write
call signal, the BSM executes one cycle, either a read or a
write cycle, depending upon which was last completed.
Since the core storage has a destructive readout, a write
cycle must always follow a read cycle in order to allow the
data to be regenerated. Interlocks are provided to ensure
that read and write cycles alternate properly. However, a
system reset resets these interlocks so that the first storage
cycle is a read cycle.
Access time, from read
call
until data is available at the
interface, is approximately 465 ns.
5410 TO
1-7
ll
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