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CPU juPD7810
BLOCK DIAGRAM
PIN CONFIGURATION
1
•I
I
LATCH
INC/OEC
SP
EA
V
B
D
E
V
B'
H1
A
c
BUFFER
I
G,R
G,R
PROGRAM
MEMORY
(MPO7811
only)
a
MEMORY
(256-BYTEI
IT
INTERNAL DATA BUS
ICO
[PSW
Si
X
ALU
8/16)
-
0
INST. REG
INST.
OECODER
Note: >jPD7810 doesn't contain program memory
(4 Kbyte).
CONTROL
CONTROL
CONTROL
I!
is
li
PAO C
PA1 C
'A2 C
PB2 C
PB3C
PB4C
PB5C
PB6C
PB7 C
PCO/TxO C
PCI/RxD C
PC2/SCK C
PC3/INT2 C
PC4/TO C
PC5/CI C
PC6/CO0 C
PC7/COJ C
MA\ C
INT1 C
MODE1 C
RESET C
MODEO C
X2 C
X1 C
2
3
4
5
6
7
8
9
0
1
2
3
4
S
7
8
9
20
21
22
23
24
25
26
27
28
29
30
31
32
^
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3VQ0
3 PD7
3 PD6
3 PD5
3 PD4
3 PD3
3 PD2
3PD1
3PD0
3 PF7
3PF6
0 PF5
3 PF4
3 PF3
0 PF2
0 PF1
0 PFO
0 ALE
0 VTE
0 R"D"
0 AVcc
0 VAREF
0 AN7
0 AN6
O AN5
O AN4
0 AN3
0 AN2
0 AN1
13 AN0
0 AVSS
GATE ARRAY MB60H144
PA7-0
PB7-0
PC7-0
PD7-0
PF7-0
NMI
MODE 0.1
PIN
: Port A
: Port B
: Port C
: Port D
: Port F
NAMES
X1, X2
AN7-0
RD
WR
ALE
: Non Maskable Interrupt
RESET
: Mode 0, 1
: Crystal
: Analog Input
,
: Read Strobe
: Write Strobe
: Address Latch Enabl
: Reset
PIN CONFIGURATION
PIN DEFINITIONS
64 63 62 61 60 S9 58 57 66 65 54 S3 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
nnnnnnnnnnnnnnnnnnnflnnnrnnnnnnnn
EJECTOR WARK
o
UUUUUUUUUJJUU
9 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin
no.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
I
I
I
I
I
I
0
I
I
I
I/O
I/O
I/O
I/O
I/O
-
Pin
name
RESE
REC
PROG
RCAN
BY IN
TRIG
BY PA
INC1
INC2
TEST
CPU 7
CPU6
CPU 5
CPU4
CPU3
VSS
Pin
no.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O
I/O
I/O
I/O
I
I
I
I
I
I
0
0
0
0
0
I
-
Pin
name
CPU2
CPU1
CPUO
CS
WR
RD
AD2
AD1
ADO
PENA
CONP
DOFF
SOFF
MUTE
CK1
VDD
Pin
no.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
Pin
name
COUT
SH
DA12
DA11
DA10
DA 9
DA8
DA 7
DA 6
DA 5
DA 4
DA 3
DA 2
DA1
CAS
VSS
Pin
no.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
I
0
-
Pin
name
WE
C138
B138
A138
A7
A1
A5
A2
A4
AO
A3
RAS
A6
DOUT
DIN
VDD
Fujitsu CMOS Gate Array "H" Version Pin Assign
-26-
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