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STATE OUTPUTS
J3
I/O
TIMING OUTPUTS
J4
< 16
< 17
< 18
<9,19
< 14
< 10
< 13
<20
<21
FROM TIMING BIT SELECT SWITCH
<22
< 15
C/D
1 -<
MSG
1
BSY
}
SEL
1
REQ
|
ACK
1
ATN
1
RST
1
TEST
CONNECTOR
DB1
i -<
DB2
I
DB3
1
DB4
1
DB5
1
DB6
1
DB7
1
DBP
1
TEST
CONNECTOR
MISC/10343B05
****** NOTICE ******
The schematic on pages A-7 through A-10 is supplied only as an aid to
understanding circuit interface characteristics. It is not intended to be
used as a service or troubleshooting aid. This schematic is NOT subject to
a revision or change program to keep it current or accurate.
ACCORDINGLY, HEWLETT-PACKARD SHALL NOT BE LIABLE
FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES, WHETHER BASED ON
CONTRACT, TORT, OR ANY OTHER LEGAL THEORY ARISING
FROM THE USE OF THIS SCHEMATIC.
Figure A-Z HP 10343B Schematic (Continued)
Additional Information
A-10
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