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7-4. Drive circuit
This circuit charges and discharges the capacitance
between the gate and the source of the power MOS
FET by receiving pulses from the oscillator. As shown
in Fig.10, the basic circuit configuration is totem-pole
type connection of transistors and the maximum source
current is 0.2A and the maximum sink current is 0.3A.
As this current can sink even when the V
lower than the shutdown voltage, the drive circuit turns
off the MOS FET without fail.
7-5. Latch circuit
The latch circuit is a circuit which keeps an output from the oscillator low and stops operation of
the power supply when overvoltage protection(OVP) and thermal shutdown(TSD) circuits are in
operation. As the sustaining current of the latch circuit is 400 A maximum when the V
voltage is 8.5V, the power supply circuit sustains the OFF-state as long as the current of 400 A
minimum flows to the V
In order to prevent a malfunction caused by noise, etc., delay time is provided by C2 incorporated
in the hybrid IC and therefore, the latch circuit operates when the OVP or TSD circuit is in opera-
tion or and external signal input is provided for 10 sec. or longer.
In addition, even after the latch circuit start operating, the constant voltage regulator(Reg) circuit is
in operation and the circuit current is at a high level. As a result, the V
decreases. When the V
starts increasing as the circuit current is below 400 A. When it reaches the operation start voltage
(16V typ), the V
terminal voltage decreases as the circuit current increases again.
IN
When the latch circuit is on, the V
voltage increases and decreases within the range
from 10V(typ) to 16V(typ) and is prevented from
abnormally increasing. Fig. 11 shows and
example of the V
terminal voltage waveform
IN
when the latch circuit is in operation.
Cancellation of the latch circuit is done by
decreasing the V
terminal voltage blow 6.5V.
IN
Usually the power supply can be restarted by
shutting down and an AC input to the power
supply once.
voltage is
IN
terminal from the start-up resistor.
IN
terminal voltage become lower than the shutdown voltage (10V typ), it
IN
terminal
IN
34
Fig. 10 Drive circuit
terminal voltage rapidly
IN
Fig. 11 Example of V
waveform at latch circuit on
terminal
IN
terminal voltage
IN
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