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COUNTER
TIMING CHART
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these in turn operates
the appropriate display indicators.
The latches are
all strobed
once per count cycle
to update the display, in the same manner
as described for Ul05.
In order
to read the incoming frequency correctly,
to the nearest 100
Hz, the counter
would have to be
gated "on" for 10 milliseconds;
however,
since we
use a prescaler
with a
divide-by-ten
ratio~we
must extend the
count cycle time to 100ms. This is accomplished
by
the clr line of UI02, the
prescaler. It operates, and passes on its output pulses, only when that line
is high;
thus,
for the time it is low,
the counters stop, but store their
~resent
count while the latches are strobed,
thu~assing
that count to them
(and the displays),
and then are preset
by
the rst line, ready to stact the
next count cycle.
Unfortunately, it takes a finite time to
(a) stop the counting, (b) transfer the count
to the
latches,
(c) clear the
counters and
(d) start the next count cycle.
This
is ac-
compli shed ,
as shown in the accompanying co-
unter timing chart,
during the
25 ms immed-
iately following
the counting portion of the
counting cycle.
This
overall
cycle trans-
lates to a rate of
eight updates of the dis-
play per seconde
For a laboratory-style frequency counter
each decade would
be
reset to zero (BeD 0000)
at the end of each complete count cycle;
but
here,
we have to
accountfor the fact that
the
frequency being counted
is 9 MHz . above
the
operating
frequency,
and for
the fact
that we have different
offsets (carrier osc-
illator frequencies) for USB and LSB operation.
This makes it necessary to
preset the counters to a number
different than zero in order to compensate.
When
operating in the USB mode,
the number to which the
counters must
00
preset
are (MSD to LSD)
09967; in the LSB mode,
it is 10000.
This is ac-
complished
by
hard-wiring the USB and LSB lines to the
appropriate load in-
puts of the counter chips,
and using the rst line
to drive the "load" con-
trol pins.
Then,
when the active
counting portion of the
count cycle
00-
gins again, eachcounter advances through zero (overflow) to a value approp-
riate for the transceiver operating frequency,
and this value is displayed.
Any carry from the MSD counter is discarded and ignored.
Another way of
stating the matter
is that
the counters are preset to
the above numbers, which correspond to a number that is 9,000.0 (or 9,003.3)
subtracted from the
overflow value
of the counter
chain,
i.e., 10000.0.
This is, in fact, a negative number, although the counter does not recognize
it as such---in this way, the counter subtractsthecarrier oscillator freq-
uency from the L.O. frequency, as is required for a correct display.
It is not necessary for the 10 MHz digit to be arrived at by a counter,
and to do so
would add unnecessary complexity
to the circuit.
Instead, it
is hard-wired such that, when the BAND switch is on the 160 through
40
meter
positions, it is extinguished;
when it is in the 20 meter position, Ql09 is
saturated and
segments B and
C
of the display
are grounded through approp-
riate current
limiting resistors,
and the
numeral
"1" is therefore dis-
played;
and in the 10 and 15 meter positions of the BAND switch,
Ql08 is
saturated,grounding the current limiting resistors for segments A, B, D, E
and
G,
thus displaying the numeral
"2".
6-3
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Troubleshooting
